Pei Luo

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Email: silenceluo at coe.neu.edu

Google site: https://sites.google.com/site/silenceluo/


EDUCATION

09/2013 - present Northeastern University, Boston, MA Ph.D. Candidate

09/2012 - 08/2013 Boston University, Boston, MA Ph.D. Candidate

09/2009 - 06/2012 Chinese Academy of Sciences (CAS), Beijing, P.R. China M.Eng. in Computer Application and Technology, Center for Space Science and Applied Research

09/2005 - 07/2009 Huazhong University of Science & Technology (HUST), Wuhan, P.R. China B.Eng. in Automation, Dept. of Control Science and Engineering [1]


EMPLOYMENT

Intel Labs, Wireless Communication Group, Internship, May 2015 – Aug. 2015

Teaching Assiant, Electrical and Computer Engineering, Boston University Fall 2012, Spring 2013

Instructor,Electrical & Electronic Innovation Center (EEIC), HUST 07/2009 – 08/2009

Co- instructor,Engineering Training Center, HUST 08/2009 – 09/2009

Teaching assistant, Electrical & Electronic Innovation Center (EEIC), HUST 07/2009 – 09/2009

Teaching assistant, Electrical & Electronic Innovation Center (EEIC), HUST 07/2008 – 09/2008



PUBLICATIONS

Pei Luo, Konstantinos Athanasiou, Yunsi Fei, Thomas Wahl, "Algebraic fault analysis of SHA-3", Design, Automation and Test in Europe (DATE), 2017

Pei Luo, Yunsi Fei, Liwei Zhang and A. Adam Ding, "Differential Fault Analysis of SHA3-224 and SHA3-256", FDTC 2016 - Thirteenth Workshop on Fault Diagnosis and Tolerance in Cryptography, Aug., 2016

Pei Luo, Cheng Li and Yunsi Fei, "Concurrent Error Detection for Reliable SHA-3 Design", In Proceedings of the 26th edition on Great Lakes Symposium on VLSI, ACM, 2016

Xin Fang, Pei Luo, Yunsi Fei, and Miriam Leeser, “Leakage Evaluation on Power Balance Countermeasure Against Side-Channel Attack on FPGAs”, 2015 IEEE High Performance Extreme Computing Conference

Chao Luo, Yunsi Fei, Pei Luo, Saoni Mukherjee and David Kaeli, "Side-channel power analysis of a GPU AES implementation", 2015 33rd IEEE International Conference on Computer Design (ICCD), pp.281-288

Liwei Zhang, A. Adam Ding, Yunsi Fei, and Pei Luo, “A Unified Metric for Quantifying Information Leakage of Cryptographic Devices under Power Analysis Attacks”, Asiacrypt 2015

Pei Luo, Liwei Zhang, A.Adam Ding, Yunsi Fei, "Towards Secure Cryptographic Software Implementation Against Side-Channel Power Analysis Attacks," 26th IEEE International Conference on Application-specific Systems, Architectures and Processors

Pei Luo, Yunsi Fei, A. Adam Ding, Xin Fang, David R. Kaeli, Miriam Leeser, "Side-Channel Analysis of MAC-Keccak Hardware Implementations", 2015 Hardware and Architectural Support for Security and Privacy (HASP)

Liwei Zhang, A. Adam Ding, Yunsi Fei, Pei Luo, "Efficient 2nd-order Power Analysis on Masked Devices Utilizing Multiple Leakage", 2015 IEEE Int. Symposium on Hardware-Oriented Security and Trust (HOST)

Pei Luo and Yunsi Fei, "Faulty Clock Detection for Crypto Circuits Against Differential Fault Analysis Attack", Cryptology ePrint Archive, Report 2014/883, 2014.

Luo, Pei; Fei, Yunsi; Fang, Xin; Ding, A.Adam; Leeser, Miriam; Kaeli, David R., "Power analysis attack on hardware implementation of MAC-Keccak on FPGAs," ReConFigurable Computing and FPGAs (ReConFig), 2014 International Conference on , vol., no., pp.1,7, 8-10 Dec. 2014

Luo, Pei; Fei, Yunsi; Zhang, Liwei; Ding, A.Adam, "Side-channel power analysis of different protection schemes against fault attacks on AES," ReConFigurable Computing and FPGAs (ReConFig), 2014 International Conference on , vol., no., pp.1,6, 8-10 Dec. 2014

Ding, A. Adam, Liwei Zhang, Yunsi Fei, and Pei Luo. "A statistical model for higher order DPA on masked devices." In Cryptographic Hardware and Embedded Systems–CHES 2014, pp. 147-169. Springer Berlin Heidelberg, 2014.

Swamy, Tushar, Neel Shah, Pei Luo, Yunsi Fei, and David Kaeli. "Scalable and efficient implementation of correlation power analysis using graphics processing units (GPUs)." In Proceedings of the Third Workshop on Hardware and Architectural Support for Security and Privacy, p. 10. ACM, 2014.

Pei Luo, Andy Yu-lun Lin, Zhen Wang, Mark Karpovsky, "Hardware implementation of reliable and secure Shamir’s secret sharing", 15th IEEE International Symposium on High Assurance Systems Engineering, 2014

Shan Li, Pei Luo, Junshe An, "航天器综合电子系统通用测试系统设计." Journal of Harbin Institute of Technology(New Series) 9 (2014): 016.

Pei Luo, Zhen Wang and Mark Karpovsky, "Secure NAND Flash Memories Resilient to Strong Fault-Injection Attacks Using Algebraic Manipulation Detection Codes", Proc. Int. Conference on Security and Management, SAM , 2013

Shizun Ge, Zhen Wang, Pei Luo, Mark Karpovsky, "Secure Memories Resistant to Both Random Errors and Fault Injection Attacks Using Nonlinear Error Correction Codes", Proc. Workshop on Hardware and Architectural Support for Security and Privacy, HASP 2013, 2013

Shizun Ge, Zhen Wang, Pei Luo, Mark Karpovsky, "Reliable and Secure Memories Based on Algebraic Manipulation Detection Codes and Robust Error Correction”, DEPEND 2013, The Sixth International Conference on Dependability

Pei Luo, Jian Zhang, “SEU Mitigation Strategies for SRAM-based FPGA”, the 4th International Symposium on Photoelectronic Detection and Imaging, Beijing China, May 2011.

Pei Luo, Guofeng Xue, Jian Zhang, Xunfeng Zhao, “A Kind Of High Reliability On-board Computer”, 2011 2nd International Congress on Computer Applications and Computational Science, Bali Indonesia, November 2011.

Pei Luo, Guofeng Xue, “基于 USB2. 0 总线的航天设备地面检测系统(Ground-Testing System for Space Equipment Based On USB Wire)”, Modern Electronic Technique, Vol. 34, No. 10, pp.123-126, 2011.

Pei Luo, Jian Zhang, “A High Reliable SOC On-board Computer based on Leon3”, 2012 IEEE International Conference on Computer Science and Automation Engineering, Zhangjiajie China, May 2012.


RESEARCH EXPERIENCE

High Speed Data Acquisition and Analysis System Based on Vistex-5 FPGA 06/2012 – 08/2012

Designed the hardware system based on PCIe/104 and Virtex-5 FPGA.

Devised the whole data acquisition and analysis system architecture.

Implemented PCIE and DDR2 to transfer and store the data rapidly.


Reconfigurable High Speed Atomic Force Microscopy System 03/2011 – 07/2012

Developed the DSP and FPGA software of the whole system.

Devised Ping-Pong buffer and DMA to accelerate the acquisition speed.

Implemented filter in FPGA to improve the precision of the acquisition system.


High Reliable SOC System Based on Leon3 Processor Core 05/2011 – 12/2011

Developed the hardware of the SOC system for Leon3 based on Virtex4 and ProASICPlus FPGAs.

Deeply studied the SPARC V8 architecture and realized Leon3 processor on the system.

Implemented Triple Module Redundancy and scrubbing of SRAM-based FPGAs to make the design reliable.


Data Acquisition & Encryption Satellite Payload System 09/2010 – 11/2010

Designed the hardware of the system, capable of dealing with the high speed data efficiently.

Studied the anti-SEU strategies for SRAM-based FPGAs and implemented them in the design.


Reconfigurable Ground-testing System for SPARC V7 & V8 On-board Computer 06/2010 – 07/2010

Devised the system based on FPGA to test the computers based on SPARC V7&V8 processors conveniently.

Applied to three important projects and tested the on-board computers successfully.


VxWorks Operating System for On-board Computer System Based On AT697 07/2010 – 08/2010

Wrote the high reliable boot loader, ported the VxWorks OS to the system.

Studied the software anti-SEU strategies and applied them in this design.


On-board Computer System Based on ERC32 04/2010 – 06/2010

Designed the reliable, fault tolerant hardware system based on SPARC V7 structure processor ERC32.

Devised the high reliable Boot Loader which can boot the OS in different ways.

Ported the VxWorks OS to the system and deeply studied it, wrote the test programs.


Reconfigurable ground-testing System for Space Equipment Based on USB2.0Wire 03/2010 – 05/2010

Worked in a two-person group and designed the reconfigurable system to test different equipments based on USB2.0 and FPGA, successfully used in the testing of three following important projects.

Studied the USB2.0 wire and developed the system which can test different kinds of interfaces, used DMA and Ping-Pong strategies to accelerate the processing speed of the system.


High-power D Class Acoustic Amplifier System 12/2009 – 01/2010

Worked in a two-person group and developed the system for Institute of Acoustics, CAS.

Successfully devised the system with the merits of high efficiency, low noise and high power.

Used in following ultrasonic wave research and several related projects.


Data Acquisition and Analysis System for Aluminum Electrolyzing Factory 07/2009 – 08/2009

Worked in a two-person group and developed the convenient handheld data acquisition and analysis equipment with the characteristics of high precision and high efficiency.

Learned the strategies of acquisition and amplification of weak signals under complex electromagnetic environment and used them in my design to deal with the weak signals in the factory.

Successfully used in aluminum electrolyzing factories to monitor the electrolyzing process.


Intelligent car based on μcos-ii 11/2008 – 12/2008

Studied the μcos-ii operating system and ported it to the Renesas M16C-62A micro controller.


An Intelligent Chatting & Nursing Robot for Children 02/2008 – 06/2008

Worked in a three-person group and developed the whole system for Intel Cup Undergraduate Electronic Design Contest – Embedded System Design Invitational Contest, won the second prize.

Studied the speech recognition & synthesis, natural language understanding, GPRS and web information mining technologies and applied them in the design. Successfully developed the system which can communicate with children in simple language and take care of them when caregivers absent.


Contributions

Reviewer for Embedded Systems Letters, IEEE

Reviewer for ACM Transactions on Embedded Computing

Reviewer for Elsevier Computers & Electrical Engineering

Program committee of ReConFig 2015 (2015 International Conference on Reconfigurable Computing and FPGAs)

Review for Security and Communication Networks, Wiley Online Library

Program committee of ReConFig 2016 (2016 International Conference on Reconfigurable Computing and FPGAs)

Reviewer for Journal of Parallel and Distributed Computing, Elsevier


HONORS & AWARDS

Zhuhai Longtec Ltd. Scholarship, 2008

China Instrument and Control Society Scholarship of 2008-2009

Intel Cup Undergraduate Electronic Design Contest – Embedded System Design Invitational Contest, the second prize.

Sony Cup National Undergraduate Electronic Design Contest, the second prize of Hubei Province of P.R. China.

Actions Semiconductor Cup Embedded System Design Contest, HUST, the first prize.

Tianyu Information Industry Cup Software Design Contest, HUST, the third prize.





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