Hardware-assisted Security

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Contents

Description

As networking connections become pervasive for computer systems and embedded software contents increase dramatically, it becomes more convenient for hostile parties to utilize software vulnerability to attack embedded systems, such as personal digital assistants (PDAs), cell phones, networked sensors, and automotive electronics.

The vulnerability of embedded systems carrying sensitive information to security attacks, ranging from common cybercrimes to terrorism, has become a very critical problem with far-reaching financial and social implications. For example, security is still the largest concern that prevents the adoption of mobile commence and secure messaging. In addition to the traditional metrics of performance, area, and power consumption, security has been regarded as one of the most important design goals for networked embedded systems.

Compared to the general purpose and commodity desktop system, an embedded system presents advantages in allowing deployment of meaningful countermeasures across system architecture design. Building a secure embedded system, however, is a complex task that requires multidisciplinary research across different system layers and spanning various design stages, including circuits, processors, Operating System (OS), compiler, system platform, etc. It is especially challenging to find efficient solutions granting system immunity to a broad range of evolving attacks, considering the stringent constraints of embedded systems on computing capability, memory, and battery power and the tamper-prone insecure environment.

Projects

People


Publications

Book Chapters

  • Y. Fei and J. C. Martinez Santos, “Security in embedded systems,” In: M. Tehranipoor and C. Wang, Eds. Introduction to Hardware Security and Trust. New York: Springer, 2012.

Journal Papers

  • J. C. Martinez Santos and Y. Fei, “Leveraging speculative architectures for run-time program validation,” ACM Trans. on Embedded Computing Systems, vol. 13, no.1, Aug. 2013.

Conference Papers

  • M. Shafaei and Y. Fei, "HiTS: A high-throughput memory scheduling scheme to mitigate denial-of-service attacks in multi-core systems" Int. Symp. on Computer Architecture and High Performance Computing (SPAC-PAD), Oct. 2014.
  • J. C. Martinez Santos and Y. Fei, "Micro-architectural support for metadata coherence in multi-core dynamic information flow tracking," Int. Workshop on Hardware & Architectural Support for Security and Privacy (HASP), in Conjunction with Int. Symp. on Computer Architecture (ISCA), June 2013.
  • J. C. Martinez Santos and Y. Fei, "Designing and implementing a malicious 8051 processor,” Proc. IEEE Int. Symp. on Defect and Fault Tolerance in VLSI & Nanotechnology Systems, Special Session on Hardware Security Session on Capture the Chip, Oct. 2012.
  • J. C. Martinez Santos, Y. Fei, and Z. J. Shi, “Static secure page allocation for light-weight dynamic information flow tracking,” Int. Conf. on Compilers, Architecture & Synthesis for Embedded Systems (CASES), Oct. 2012.
  • J. C. Martinez Santos, Y. Fei, and Z. J. Shi, “PIFT: Efficient dynamic information flow tracking using secure page allocation,” in WkShp on Embedded System Security (WESS) (held in conjunction with Embedded Systems Week), Oct. 2009.
  • J. C. Martinez Santos and Y. Fei, “Leveraging speculative architectures for run-time program validation,” in Proc. IEEE Int. Conf. Computer Design, Oct. 2008.




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