Conferences and Workshops papers

From NUEESS

== This page has not been updated actively. Please refer to Prof. Yunsi Fei's Google Scholar record for updates: https://scholar.google.com/citations?user=Ja64KW4AAAAJ&hl=en ==

2017

Z. Jiang, Y. Fei, and D. R. Kaeli, “A novel side-channel timing attack on GPUs,” Great Lake Symp. on VLSI (GLSVLSI), May 2017.
C. Luo, Y. Fei, and A. Ding, “Side-channel power analysis of XTS-AES,” Proc. Design Automation & Test in Europe (DATE), Mar. 2017.
P. Luo, K. Athanasiou, Y. Fei, and T. Wahl, “Algebraic fault analysis of SHA-3,” Proc. Design Automation & Test in Europe (DATE), Mar. 2017.

2016

Y. M. Aval, Y. Han, A. Tu, S. Basagni, M. Stojanovic, and Y. Fei, “Testbed-based performance evaluation of handshake-free MAC protocols for underwater acoustic sensor networks,” MTS/IEEE Proc. Oceans, Sept. 2016.
P. Luo, Y. Fei, L. Zhang, and A. A. Ding, “Differential fault analysis of SHA3-224 and SHA3-256,” Int. WkShp on Fault Diagnosis and Tolerance in Cryptography (FDTC), Aug. 2016.
Y. Han, Y. Fei, and A. A. Ding, “A stochastic MAC protocol with randomized power control for underwater sensor networks,” IEEE Int. Conf. on Sensing, Communication and Networking (SECON), June 2016.
P. Luo, C. Li, and Y. Fei, “Concurrent error detection for reliable SHA-3 design,” Great Lake Symp. on VLSI (GLSVLSI), May 2016.
Z. Jiang, Y. Fei, and D. R. Kaeli, “A complete key recovery timing attack on a GPU,” Int. Symp. High Performance Computer Architecture (HPCA), Mar. 2016.

2015

L. Zhang, A. A. Ding, Y. Fei, and P. Luo, “A Unified Metric for Quantifying Information Leakage of Cryptographic Devices under Power Analysis Attacks,” Int. Conf. on the Theory and Application of Cryptology and Information Security (AsiaCrypt), Nov.-Dec. 2015.
C. Luo, Y. Fei, P. Luo, S. Mukherjee, and D. Kaeli, “Side-channel power analysis of a GPU AES implementation,” Int. Conf. Computer Design (ICCD), Oct. 2015.
Y. Han and Y. Fei, “TARS: A Traffic-Adaptive Receiver-Synchronized MAC Protocol for Underwater Sensor Networks,” Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), Best Paper Award, Oct. 2015.
P. Luo, L. Zhang, Y. Fei, and A. A. Ding "Towards Secure Cryptographic Software Implementation Against Side-Channel Power Analysis Attacks", Int. Conf. on Application-specific Systems, Architectures, and Processors (ASAP), July 2015.
X. Fang, Y. Fei, and M. Leeser, "Balance Power Leakage to Fight Against Side-Channel Analysis at Gate Level in FPGAs", Int. Conf. on Application-specific Systems, Architectures, and Processors (ASAP), July 2015.
P. Luo, Y. Fei, X. Fang, A. Adam Ding, D. R. Kaeli, and M. Leeser, “Side-channel analysis of MAC-Keccak hardware implementations,” in Wkshp on Hardware and Architectural Support for Security & Privacy (HASP), in conjunction with Int. Symp. Computer Architecture, June 2015.
L. Zhang, A. A. Ding, Y. Fei, and P. Luo, “Efficient 2nd-order power analysis on masked devices utilizing multiple leakage,” Proc. IEEE Int. Symp. on Hardware Oriented Security & Trust (HOST), May 2015.
B. Jiang and Y. Fei, "Traffic and Vehicle Speed Prediction with Neural Network and Hidden Markov Model in Vehicular Networks," Proc. IEEE Intelligent Vehicles Symp. (IV'15), June, 2015.
Y. Han and Y. Fei, “A delay-aware probability-based MAC protocol for underwater acoustic sensor networks,” to appear, Proc. Int. Conf. on Computing, Networking and Communications, Wireless Ad Hoc and Sensor Networks Symposium (ICNC-WAHS), Feb. 2015.

2014

P. Luo, Y. Fei, X. Fang, A. A. Ding, M. Leeser, and D. R. Kaeli, “Power analysis attack on hardware implementation of MAC-Keccak on FPGAs,” Proc. Int. Conf. on Reconfigurable Computing and FPGAs (ReConfig’14), Dec. 2014.
P. Luo, Y. Fei, L. Zhang, and A. A. Ding, “Side-channel power analysis of different protection schemes against fault attacks on AES,” Proc. Int. Conf. on Reconfigurable Computing and FPGAs (ReConfig’14), Dec. 2014.
M. Sabbagh, Y. Fei, T. Wahl, and A. Ding, “SCADET: A side-channel attack detection tool for tracking Prime+Probe,” ACM Int. Conf. Computer-aided Design (ICCAD), Nov. 2018. M. Shafaei and Y. Fei, "HiTS: A high-throughput memory scheduling scheme to mitigate denial-of-service attacks in multi-core systems" Int. Symp. on Computer Architecture and High Performance Computing (SPAC-PAD), Oct. 2014.
A. A. Ding, L. Zhang, Y. Fei, and P. Luo "A statistical model for multivariate DPA on masked devices," Proc. Int. Wksp on Cryptographic Hardware & Embedded Systems (CHES), Sept. 2014.
T. Swamy, N. Shah, P. Luo, Y. Fei, and D. Kaeli, "Scalable and efficient implementation of correlation power analysis using Graphic Processing Units (GPUs)," in Wkshp on Hardware and Architectural Support for Security & Privacy (HASP), in conjunction with Int. Symp. Computer Architecture, June 2014.
B. Jiang and Y. Fei, "On-road PHEV power management with hierarchical strategies in vehicular networks," Proc. IEEE Intelligent Vehicles Symp. (IV'14), June, 2014.

2013

J. C. Martinez Santos and Y. Fei, "Micro-architectural support for metadata coherence in multi-core dynamic information flow tracking," Int. Workshop on Hardware & Architectural Support for Security and Privacy (HASP), in Conjunction with Int. Symp. on Computer Architecture (ISCA), June 2013.
B. Jiang and Y. Fei, "Decentralized scheduling of PEV on-street parking and charging for smart grid reactive power compensation," Proc. IEEE PES Innovative Smart Grid Technologies (ISGT), Feb. 2013.

2012

J. C. Martinez Santos and Y. Fei, "Designing and implementing a malicious 8051 processor,” Proc. IEEE Int. Symp. on Defect and Fault Tolerance in VLSI & Nanotechnology Systems, Special Session on Hardware Security Session on Capture the Chip, Oct. 2012.
J. C. Martinez Santos, Y. Fei, and Z. J. Shi, “Static secure page allocation for light-weight dynamic information flow tracking,” Int. Conf. on Compilers, Architecture & Synthesis for Embedded Systems (CASES), Oct. 2012.
Y. Fei, Q. Luo, and A. A. Ding, “A statistical model for DPA with novel algorithmic confusion analysis,” Proc. Int. Wksp on Cryptographic Hardware & Embedded Systems(CHES), Sept. 2012.
T. Hu and Y. Fei, “MURAO: A multi-level routing protocol for acoustic-optical hybrid underwater wireless sensor networks,” Proc. IEEE Communications Society Conf. on Sensor, Mesh, and Ad Hoc Communications and Networks (SECON), June, 2012.

2011

X. Guan and Y. Fei, “Adaptive extended min-sum algorithm for nonbinary LDPC decoding, ” Proc. IEEE GLOBECOM, Dec. 2011.

B. Jiang and Y. Fei, “Dynamic residential demand response and distributed generation management in smart microgrid with hierarchical agents,” Proc. Int. Conf. on Smart Grid & Clean Energy Technologies, Sept. 2011.

Q. Luo and Y. Fei, “Algorithmic collision analysis of evaluating cryptographic systems and side-channel attacks,” Proc. IEEE Int. Symp. on Hardware Oriented Security & Trust (HOST), June 2011.

2010

T. Hu and Y. Fei, “An adaptive and energy-efficient routing protocol based on machine learning for underwater delay tolerant networks,” ACM/IEEE Int. Symp. on Modeling, Analysis, and Simulation of Computer & Telecommunication Systems (MASCOTS), Aug. 2010.

H. Lin and Y. Fei, “Exploring custom instruction synthesis for application-specific instruction set processors with multiple design objectives,” IEEE Int. Symp. on Low Power Electronics & Design, Aug. 2010.

H. Lin and Y. Fei, “A novel multi-objective instruction synthesis flow for application-specific instruction set processors,” ACM Proc. Great Lakes Symp. VLSI, May 2010.

2009

J. C. Martinez Santos, Y. Fei, and Z. J. Shi, “PIFT: Efficient dynamic information flow tracking using secure page allocation,” in WkShp on Embedded System Security (WESS) (held in conjunction with Embedded Systems Week), Oct. 2009.

H. Lin and Y. Fei, “Resource sharing of pipelined custom hardware extension for energy-efficient application-specific instruction set processor,” in Proc. IEEE Int. Conf. Computer Design, Oct. 2009.

X. Guan, Y. Fei, and H. Lin, “A hierarchical design of application-specific instruction set processors for high-throughput FFT,” in Proc. IEEE Int. Symp. on Circuits and Systems, May 2009.

X. Guan, H. Lin, and Y. Fei, “Design of an application-specific instruction set processor for high-throughput and scalable FFT,” in Proc. IEEE Design Automation & Test in Europe Conf., Apr. 2009.

H. Yan, Z. J. Shi, and Y. Fei, “Efficient implementation of Elliptic Curve Cryptography on DSP for underwater sensor networks,” WkShp on Optimizations for DSP & Embedded Systems (held in conjunction with IEEE/ACM Int. Symp. on Code Generation & Optimization), Mar. 2009.

2008

T. Hu and Y. Fei, “QELAR - A Q-learning-based energy-efficient and lifetime-aware routing protocol for underwater sensor networks,” in IEEE Int. Performance Computing & Communications Conf., Dec. 2008.

J. C. Martinez Santos and Y. Fei, “Leveraging speculative architectures for run-time program validation,” in Proc. IEEE Int. Conf. Computer Design, Oct. 2008.

V. Kundeti, Y. Fei, and Sanguthevar Rajasekaran, “An efficient digital circuit for implementing sequence alignment algorithm in an extended processor,” in IEEE Int. Conf. Application-specific Systems, Architectures & Processors, July 2008.

X. Guan and Y. Fei, “Reducing power consumption of embedded processors through register file partitioning and compiler support,” in IEEE Int. Conf. Application-specific Systems, Architectures & Processors, July 2008.

H. Lin, G. Sun. Y. Fei, Y. Xie, and A. Sivasubramaniam, “Thermal-aware design considerations for application-specific instruction set processor,” in IEEE Symp. on Application Specific Processors, June, 2008.

H. Lin and Y. Fei, “Harnessing horizontal parallelism and vertical instruction packing of programs to improve system overall efficiency,” in Proc. IEEE Design Automation & Test in Europe Conf., Mar. 2008.

2007

H. Lin, X. Guan, Y. Fei, and Z. Shi, “Compiler-assisted architectural support for program code integrity monitoring in application-specific instruction set processors,” in IEEE Int. Conf. on Computer Design, Oct. 2007.

Y. Fei, H. D. Lin, and X. Guan, “A hardware/software cooperative approach for reducing memory traffic in application-specific instruction set processors,” in IEEE Int. Midwest Symp. on Circuits & Systems, Aug. 2007.

Y. Fei and Z. Shi, “Microarchitectural support for program code integrity monitoring in application-specific instruction set processors,” in Proc. IEEE Design Automation & Test in Europe Conf., Apr. 2007.

H. Lin and Y. Fei, “Utilizing custom registers in application-specific instruction set processors for register spills elimination,” in Proc. ACM Great Lakes Symp. on VLSI, Mar. 2007.

Y. Fei and Z. Shi, “Embedding program code integrity monitoring in application-specific instruction set processors,” in Annual Boston Area Computer Architecture Workshop (BARC), Jan. 2007.

H. D. Lin and Y. Fei, “Custom register binding in application-specific instruction set processors to eliminate register spills,” in Annual Boston Area Computer Architecture Workshop (BARC), Jan. 2007.

2006

Z. Shi and Y. Fei, “Exploring architectural challenges in scalable underwater wireless sensor networks,” in Annual Boston Area Computer Architecture Workshop (BARC), Feb., 2006.

2004

Y. Fei, L. Zhong, and N. K. Jha, “An energy-aware framework for coordinated dynamic software management in mobile computers,” in ACM/IEEE Int. Symp. on Modeling, Analysis, and Simulation of Computer & Telecommunication Systems (MASCOTS), Oct. 2004.

Y. Fei, S. Ravi, A. Raghunathan, and N. K. Jha, “Energy-optimizing source code transformations for OS-driven embedded software,” in Proc. IEEE International Conference on VLSI Design, Jan. 2004.

2003

W. Wang, T. K. Tan, J. Luo, Y. Fei, L. Shang, K. S. Vallerio, L. Zhong, A. Raghunathan, and N. K. Jha, “A comprehensive high-level synthesis system for control-flow intensive behaviors,” in Proc.IEEE Great Lakes Symposium on VLSI, April 2003.

Y. Fei, S. Ravi, A. Raghunathan, and N. K. Jha, “Energy estimation for extensible processors,” in Proc. IEEE Design Automation & Test in Europe Conference, Mar. 2003.

2002

L. Zhong, J. Luo, Y. Fei, and N. K. Jha, “Register binding based power management for high-level synthesis of control-flow intensive behaviors,” in Proc. IEEE Int. Conf. Computer Design, Sept. 2002.

Y. Fei and N. K. Jha, “Functional partitioning for low-power distributed systems of systems-on-a-chip,” in Proc. IEEE Asia South Pacific Design Automation Conference, Jan.2002.

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