Publications
From NUEESS
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| + | = Book Chapters = | ||
| + | *<section begin=yfb2 />Y. Fei, T. Eisenbarth, and D. Serpanos: Guest Editorial: Special Section on Embedded System Security. Embedded System Letters 7(1): 2015. <section end=yfb2 /> | ||
| + | *<section begin=yfb1 />Y. Fei and J. C. Martinez Santos, “Security in embedded systems,” In: M. Tehranipoor and C. Wang, Eds. ''Introduction to Hardware Security and Trust''. New York: Springer, 2012. <section end=yfb1 /> | ||
| + | |||
= Journal Papers = | = Journal Papers = | ||
| - | *X. Guan, Y. Fei, and H. Lin, “Hierarchical design of an application-specific instruction set processor for high-throughput and scalable FFT processing,” | + | |
| - | *H. Lin, Y. Fei, X. Guan, and Z. J. Shi, “Architectural enhancement and system software support for program code integrity monitoring in application-specific instruction set processors,” IEEE Trans. on VLSI,vol. 18, no. 11, pp. 1319 - 1332, Nov. 2010. | + | *<section begin=clj1 />C. Luo, Y. Fei, L. Zhang, A. A. Ding, P. Luo, S. Mukherjee, and D. Kaeli, “Power analysis attack of an AES GPU implementation,” Springer. J. Hardware & System Security (HASS), Vol. 2, No. 1, pp. 69-82, Mar. 2018.<section end=clj1 /> |
| - | *X. Guan and Y. Fei, “Register file partitioning and compiler support for reducing power consumption in embedded processors,” IEEE Trans. on VLSI, vol. 18, no. 8, pp. 1248 - 1252, Aug. 2010. | + | *<section begin=plj2 /> P. Luo, K. Athanasiou, Y. Fei, and T. Wahl, “Algebraic fault analysis of SHA-3 under relaxed fault models,” IEEE Trans. on Information Forensics and Security, Vol. 13, No. 7, July 2018. <section end=plj2 /> |
| - | *T. Hu and Y. Fei, “QELAR: A machine-learning-based adaptive routing protocol for energy efficient and lifetime-extended underwater sensor networks,” IEEE Trans. on Mobile Computing, vol. 9, no. 6, June 2010. | + | *<section begin=yhj2 /> Y. Han and Y. Fei, “TARS: A traffic-adaptive receiver-synchronized medium access control protocol for underwater sensor networks”, ACM Trans. On Sensor Networks (TOSN), vol. 13(4), pp. 27:1-27:25, Dec. 2017. <section end=yhj2 /> |
| - | *X. Guan and Y. Fei, “Register file partitioning and re-compilation for register file power reduction,” ACM Trans. on Design Automation of Electronic Systems, vol. 15, no. 3, May 2010. | + | *<section begin=bjj3 /> B. Jiang and Y. Fei, “A PHEV power management cyber-physical system for on-road applications,” IEEE Trans. On Vehicular Technology (TVT), vol. 66, no. 7, pp. 5797-6807, July 2017. <section end=bjj3 /> |
| - | *H. Lin and Y. Fei, “Orchestrating horizontal parallelism and vertical instruction packing of programs to improve system overall efficiency,” IEEE Trans. on Computers, vol. 58, no. 9, pp. 1211-1220, Sept. 2009. | + | *<section begin=bjj2 />B. Jiang and Y. Fei, “Vehicle speed prediction by two-level data driven models in vehicular networks,” ''IEEE Trans. Intelligent Transportation Systems'', vol. 18, no. 7, pp. 1793-1801, July 2017. <section end=bjj2 /> |
| - | *Y. Fei, L. Zhong, and N. K. Jha, “An energy-aware framework for dynamic software management in mobile computing systems,” ACM Trans. on Embedded Computing Systems, vol. 7, no. 3, Apr. 2008. | + | *<section begin=plj1 />P. Luo, Y. Fei, L. Zhang, and A. A. Ding, “Differential fault analysis of SHA-3 under relaxed fault models,” Springer. J. Hardware & System Security (HASS), vol. 1, no. 2, pp. 156-172, June 2017.<section end=plj1 /> |
| - | *Y. Fei, S. Ravi, A. Raghunathan, and N. K. Jha, “Energy-optimizing source code transformations for operating system driven embedded software,” ACM Trans. on Embedded Computing Systems, vol. 7, no. 1, Dec. 2007. | + | *<section begin=yhj1 />Y. Han and Y. Fei, “DAP-MAC: A delay-aware probability-based MAC protocol for underwater acoustic sensor networks,"''Elsevier Ad Hoc Networks (ADHOC)'', vol. 48, pp.80-92, Sept. 2016.<section end=yhj1 /> |
| - | *Y. Fei and N. K. Jha, “Integrated functional partitioning and synthesis for low power distributed systems of systems-on-a-chip,” invited paper, Special Issue on Hardware-software Codesign for SOC in Int. Journal Embedded Systems, Vol.1, Nos.1/2, pp.2-13, 2005 | + | *<section begin=yfj6 />Y. Fei, A. Ding, J. Lao, and L. Zhang, “A statistics-based success rate model for DPA and CPA,"''Journal of Cryptographic Engineering'', vol. 5, no.4, pp.227-243, Nov. 2015.<section end=yfj6 /> |
| - | *J. Luo, L. Zhong, Y. Fei, and N. K. Jha, “Register binding based RTL power management for control-flow intensive designs,” IEEE Trans. on Computer-aided Design of Integrated Circuits and Systems, vol. 23, no. 8, Aug. 2004. | + | *<section begin=bjj1 />B. Jiang and Y. Fei, “Smart home in smart microgrid: A cost-effective energy ecosystem with intelligent hierarchical agents,”''IEEE Trans. on Smart Grid'', vol. 6, no.1, pp.3-13, Jan. 2015.<section end=bjj1 /> |
| - | *Y. Fei, S. Ravi, A. Raghunathan, and N. K. Jha, “A hybrid energy estimation technique for extensible processors,” IEEE Trans. on Computer-aided Design of Integrated Circuits and Systems, vol. 23, no. 5, pp. 652-664, May 2004. | + | *<section begin=ding2014 />A. A. Ding, L. Zhang, Y. Fei, and P. Luo, “A statistical model for higher order DPA on masked devices,” IACR ePrint, 2014/433. (https://eprint.iacr.org/2014/433.pdf). <section end=ding2014 /> |
| - | *Y. Fei, X. Zheng, H. Zhang, Y. Guo, and B. Zhou, “A novel scheme of power equalization and power management in WDM all-optical networks,” IEEE Photon. Technol. Lett., vol. 11, no. 9, pp.1189-1191, Sept.1999. | + | *<section begin=fei2014 />Y. Fei, A. A. Ding, J. Lao and L. Zhang, “A statistics-based fundamental model for side-channel attack analysis,” IACR ePrint, 2014/152. (https://eprint.iacr.org/2014/152.pdf). <section end=fei2014 /> |
| + | *<section begin=jcj1 />J. C. Martinez Santos and Y. Fei, “Leveraging speculative architectures for run-time program validation,” ACM Trans. on Embedded Computing Systems, vol. 13, no.1, Aug. 2013. <section end=jcj1 /> | ||
| + | *<section begin=hlj4 />H. Lin and Y. Fei, “Resource sharing of pipelined custom hardware extension for energy-efficient application-specific instruction set processor design,” ACM Trans. on Design Automation of Electronic Systems, vol. 17, no.4, Oct. 2012. <section end=hlj4 /> | ||
| + | *<section begin=hlj3 />H. Lin, T. Hu, and Y. Fei, “Utilizing custom registers in application-specific instruciton set processors for register spill elimination,” ACM Trans. on Design Automation of Electronic Systems, vol. 17, no.4, Oct. 2012. <section end=hlj3 /> | ||
| + | *<section begin=xgj3 />X. Guan, Y. Fei, and H. Lin, “Hierarchical design of an application-specific instruction set processor for high-throughput and scalable FFT processing,” IEEE Trans. on VLSI, vol. 20, no.3, pp. 551-563, Mar. 2012. <section end=xgj3 /> | ||
| + | *<section begin=hlj2 />H. Lin, Y. Fei, X. Guan, and Z. J. Shi, “Architectural enhancement and system software support for program code integrity monitoring in application-specific instruction set processors,” IEEE Trans. on VLSI,vol. 18, no. 11, pp. 1319 - 1332, Nov. 2010. <section end=hlj2 /> | ||
| + | *<section begin=xgj2 />X. Guan and Y. Fei, “Register file partitioning and compiler support for reducing power consumption in embedded processors,” IEEE Trans. on VLSI, vol. 18, no. 8, pp. 1248 - 1252, Aug. 2010. <section end=xgj2 /> | ||
| + | *<section begin=thj1 />T. Hu and Y. Fei, “QELAR: A machine-learning-based adaptive routing protocol for energy efficient and lifetime-extended underwater sensor networks,” IEEE Trans. on Mobile Computing, vol. 9, no. 6, June 2010. <section end=thj1 /> | ||
| + | *<section begin=xgj1 />X. Guan and Y. Fei, “Register file partitioning and re-compilation for register file power reduction,” ACM Trans. on Design Automation of Electronic Systems, vol. 15, no. 3, May 2010. <section end=xgj1 /> | ||
| + | *<section begin=hlj1 />H. Lin and Y. Fei, “Orchestrating horizontal parallelism and vertical instruction packing of programs to improve system overall efficiency,” IEEE Trans. on Computers, vol. 58, no. 9, pp. 1211-1220, Sept. 2009. <section end=hlj1 /> | ||
| + | *<section begin=yfj5 />Y. Fei, L. Zhong, and N. K. Jha, “An energy-aware framework for dynamic software management in mobile computing systems,” ACM Trans. on Embedded Computing Systems, vol. 7, no. 3, Apr. 2008. <section end=yfj5 /> | ||
| + | *<section begin=yfj4 />Y. Fei, S. Ravi, A. Raghunathan, and N. K. Jha, “Energy-optimizing source code transformations for operating system driven embedded software,” ACM Trans. on Embedded Computing Systems, vol. 7, no. 1, Dec. 2007. <section end=yfj4 /> | ||
| + | *<section begin=yfj3 />Y. Fei and N. K. Jha, “Integrated functional partitioning and synthesis for low power distributed systems of systems-on-a-chip,” invited paper, Special Issue on Hardware-software Codesign for SOC in Int. Journal Embedded Systems, Vol.1, Nos.1/2, pp.2-13, 2005. <section end=yfj3 /> | ||
| + | *<section begin=jlj1 />J. Luo, L. Zhong, Y. Fei, and N. K. Jha, “Register binding based RTL power management for control-flow intensive designs,” IEEE Trans. on Computer-aided Design of Integrated Circuits and Systems, vol. 23, no. 8, Aug. 2004. <section end=jlj1 /> | ||
| + | *<section begin=yfj2 />Y. Fei, S. Ravi, A. Raghunathan, and N. K. Jha, “A hybrid energy estimation technique for extensible processors,” IEEE Trans. on Computer-aided Design of Integrated Circuits and Systems, vol. 23, no. 5, pp. 652-664, May 2004. <section end=yfj2 /> | ||
| + | *<section begin=yfj1 />Y. Fei, X. Zheng, H. Zhang, Y. Guo, and B. Zhou, “A novel scheme of power equalization and power management in WDM all-optical networks,” IEEE Photon. Technol. Lett., vol. 11, no. 9, pp.1189-1191, Sept.1999. <section end=yfj1 /> | ||
= Conferences and Workshops Papers = | = Conferences and Workshops Papers = | ||
| - | *X. Guan and Y. Fei, “Adaptive extended min-sum algorithm for nonbinary LDPC decoding, ” | + | |
| - | *B. Jiang and Y. Fei, | + | |
| - | *Q. Luo and Y. Fei, “Algorithmic collision analysis of evaluating cryptographic systems and side-channel attacks,” Proc. IEEE Int. Symp. on Hardware Oriented Security & Trust (HOST), June 2011. | + | *<section begin=ekc1 />E. Karimi, Z.H. Jiang, D. Kaeli, and Y. Fei, “A timing side-channel attack on a mobile GPU,” IEEE Int. Conf. Computer Design (ICCD), Oct. 2018 <section end=ekc1 /> |
| - | *T. Hu and Y. Fei, “An adaptive and energy-efficient routing protocol based on machine learning for underwater delay tolerant networks,” ACM/IEEE Int. Symp. on Modeling, Analysis, and Simulation of Computer & Telecommunication Systems (MASCOTS), Aug. 2010. | + | *<section begin=msc1 />M. Sabbagh, Y. Fei, T. Wahl, and A. Ding, “SCADET: A side-channel attack detection tool for tracking Prime+Probe,” ACM Int. Conf. Computer-aided Design (ICCAD), Nov. 2018. <section end=msc1 /> |
| - | *H. Lin and Y. Fei, “Exploring custom instruction synthesis for application-specific instruction set processors with multiple design objectives,” IEEE Int. Symp. on Low Power Electronics & Design, Aug. 2010. | + | *<section begin=clc4 />C. Luo, Y. Fei, and D. Kaeli, “Effective simple-power analysis attacks of Elliptic Curve Cryptography on embedded systems,” ACM Int. Conf. Computer-aided Design (ICCAD), Nov. 2018. <section end=clc4 /> |
| - | *H. Lin and Y. Fei, “A novel multi-objective instruction synthesis flow for application-specific instruction set processors,” ACM Proc. Great Lakes Symp. VLSI, May 2010. | + | *<section begin=clc3 />C. Luo, Y. Fei, and D. Kaeli, “GPU acceleration of RSA is vulnerable to side-channel timing attacks,” ACM Int. Conf. Computer-aided Design (ICCAD), Nov. 2018. <section end=clc3 /> |
| - | *J. C. Martinez Santos, Y. Fei, and Z. J. Shi, “PIFT: Efficient dynamic information flow tracking using secure page allocation,” in WkShp on Embedded System Security (WESS) (held in conjunction with Embedded Systems Week), Oct. 2009. | + | *<section begin=adc2 />A. Adam Ding, L. Zhang, F. Durvaux, F-X. Standaert, and Y. Fei, “Toward sound and optimal leakage detection procedure,” Smart Card Research and Advanced Application Conference (CARDIS), Nov. 2017. <section end=adc2 /> |
| - | *H. Lin and Y. Fei, “Resource sharing of pipelined custom hardware extension for energy-efficient application-specific instruction set processor,” in Proc. IEEE Int. Conf. Computer Design, Oct. 2009. | + | *<section begin=zjc3 /> Z. Jiang and Y. Fei, “A novel cache bank timing attack”, ACM Int. Conf. Computer-Aided Design (ICCAD), Nov. 2017. <section end=zjc3 /> |
| - | *X. Guan, Y. Fei, and H. Lin, “A hierarchical design of application-specific instruction set processors for high-throughput FFT,” in Proc. IEEE Int. Symp. on Circuits and Systems, May 2009. | + | *<section begin=plc8 />Pei Luo, Konstantinos Anthansiou, Liwei Zhang, Zhen Jiang, Yunsi Fei, A. Adam Ding and Thomas Wahl, “A First Step Towards Automatic Compiler Assisted Threshold Implementation Design,” IEEE Int. Conf. on Computer Design (ICCD), Nov. 2017. <section end=plc8 /> |
| - | *X. Guan, H. Lin, and Y. Fei, “Design of an application-specific instruction set processor for high-throughput and scalable FFT,” in Proc. IEEE Design Automation & Test in Europe Conf., Apr. 2009. | + | *<section begin=zjc2 /> Z. Jiang, Y. Fei, and D. R. Kaeli, “A novel side-channel timing attack on GPUs,” Great Lake Symp. on VLSI (GLSVLSI), May 2017. <section end=zjc2 /> |
| - | *H. Yan, Z. J. Shi, and Y. Fei, “Efficient implementation of Elliptic Curve Cryptography on DSP for underwater sensor networks,” WkShp on Optimizations for DSP & Embedded Systems (held in conjunction with IEEE/ACM Int. Symp. on Code Generation & Optimization), Mar. 2009. | + | *<section begin=clc2 /> C. Luo, Y. Fei, and A. Ding, “Side-channel power analysis of XTS-AES,” Proc. Design Automation & Test in Europe (DATE), Mar. 2017. <section end=clc2 /> |
| - | *T. Hu and Y. Fei, “QELAR - A Q-learning-based energy-efficient and lifetime-aware routing protocol for underwater sensor networks,” in IEEE Int. Performance Computing & Communications Conf., Dec. 2008. | + | *<section begin=plc7 /> P. Luo, K. Athanasiou, Y. Fei, and T. Wahl, “Algebraic fault analysis of SHA-3,” Proc. Design Automation & Test in Europe (DATE), Mar. 2017. <section end=plc7 /> |
| - | *J. C. Martinez Santos and Y. Fei, “Leveraging speculative architectures for run-time program validation,” in Proc. IEEE Int. Conf. Computer Design, Oct. 2008. | + | *<section begin=yhc4 /> Y. M. Aval, Y. Han, A. Tu, S. Basagni, M. Stojanovic, and Y. Fei, “Testbed-based performance evaluation of handshake-free MAC protocols for underwater acoustic sensor networks,” MTS/IEEE Proc. Oceans, Sept. 2016. <section end=yhc4 /> |
| - | *V. Kundeti, Y. Fei, and Sanguthevar Rajasekaran, “An efficient digital circuit for implementing sequence alignment algorithm in an extended processor,” in IEEE Int. Conf. Application-specific Systems, Architectures & Processors, July 2008. | + | *<section begin=plc6 /> P. Luo, Y. Fei, L. Zhang, and A. A. Ding, “Differential fault analysis of SHA3-224 and SHA3-256,” Int. WkShp on Fault Diagnosis and Tolerance in Cryptography (FDTC), Aug. 2016. <section end=plc6 /> |
| - | *X. Guan and Y. Fei, “Reducing power consumption of embedded processors through register file partitioning and compiler support,” in IEEE Int. Conf. Application-specific Systems, Architectures & Processors, July 2008. | + | *<section begin=yhc3 /> Y. Han, Y. Fei, and A. A. Ding, “A stochastic MAC protocol with randomized power control for underwater sensor networks,” IEEE Int. Conf. on Sensing, Communication and Networking (SECON), June 2016. <section end=yhc3 /> |
| - | *H. Lin, G. Sun. Y. Fei, Y. Xie, and A. Sivasubramaniam, “Thermal-aware design considerations for application-specific instruction set processor,” in IEEE Symp. on Application Specific Processors, June, 2008. | + | *<section begin=plc5 /> P. Luo, C. Li, and Y. Fei, “Concurrent error detection for reliable SHA-3 design,” Great Lake Symp. on VLSI (GLSVLSI), May 2016. <section end=plc5 /> |
| - | *H. Lin and Y. Fei, “Harnessing horizontal parallelism and vertical instruction packing of programs to improve system overall efficiency,” in Proc. IEEE Design Automation & Test in Europe Conf., Mar. 2008. | + | *<section begin=zhjc1 /> Z. Jiang, Y. Fei, and D. R. Kaeli, “A complete key recovery timing attack on a GPU,” Int. Symp. High Performance Computer Architecture (HPCA), Mar. 2016. <section end=zhjc1 /> |
| - | *H. Lin, X. Guan, Y. Fei, and Z. Shi, “Compiler-assisted architectural support for program code integrity monitoring in application-specific instruction set processors,” in IEEE Int. Conf. on Computer Design, Oct. 2007. | + | *<section begin=lzhc2 /> L. Zhang, A. A. Ding, Y. Fei, and P. Luo, “A Unified Metric for Quantifying Information Leakage of Cryptographic Devices under Power Analysis Attacks,” Int. Conf. on the Theory and Application of Cryptology and Information Security (AsiaCrypt), Nov.-Dec. 2015. <section end=lzhc2 /> |
| - | *Y. Fei, H. D. Lin, and X. Guan, “A hardware/software cooperative approach for reducing memory traffic in application-specific instruction set processors,” in IEEE Int. Midwest Symp. on Circuits & Systems, Aug. 2007. | + | *<section begin=clc1 /> C. Luo, Y. Fei, P. Luo, S. Mukherjee, and D. Kaeli, “Side-channel power analysis of a GPU AES implementation,” Int. Conf. Computer Design (ICCD), Oct. 2015. <section end=clc1 /> |
| - | *Y. Fei and Z. Shi, “Microarchitectural support for program code integrity monitoring in application-specific instruction set processors,” in Proc. IEEE Design Automation & Test in Europe Conf., Apr. 2007. | + | *<section begin=yhc2 /> Y. Han and Y. Fei, “TARS: A Traffic-Adaptive Receiver-Synchronized MAC Protocol for Underwater Sensor Networks,” Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), '''Best Paper Award''', Oct. 2015. <section end=yhc2 /> |
| - | *H. Lin and Y. Fei, “Utilizing custom registers in application-specific instruction set processors for register spills elimination,” in Proc. ACM Great Lakes Symp. on VLSI, Mar. 2007. | + | *<section begin=plc4 /> P. Luo, L. Zhang, Y. Fei, and A. A. Ding "Towards Secure Cryptographic Software Implementation Against Side-Channel Power Analysis Attacks", Int. Conf. on Application-specific Systems, Architectures, and Processors (ASAP), July 2015. <section end=plc4 /> |
| - | *Y. Fei and Z. Shi, “Embedding program code integrity monitoring in application-specific instruction set processors,” in Annual Boston Area Computer Architecture Workshop (BARC), Jan. 2007. | + | *<section begin=xfc1 /> X. Fang, Y. Fei, and M. Leeser, "Balance Power Leakage to Fight Against Side-Channel Analysis at Gate Level in FPGAs", Int. Conf. on Application-specific Systems, Architectures, and Processors (ASAP), July 2015. <section end=xfc1 /> |
| - | *H. D. Lin and Y. Fei, “Custom register binding in application-specific instruction set processors to eliminate register spills,” in Annual Boston Area Computer Architecture Workshop (BARC), Jan. 2007. | + | *<section begin=plc3 /> P. Luo, Y. Fei, X. Fang, A. Adam Ding, D. R. Kaeli, and M. Leeser, “Side-channel analysis of MAC-Keccak hardware implementations,” in Wkshp on Hardware and Architectural Support for Security & Privacy (HASP), in conjunction with Int. Symp. Computer Architecture, June 2015. <section end=plc3 /> |
| - | *Z. Shi and Y. Fei, “Exploring architectural challenges in scalable underwater wireless sensor networks,” in Annual Boston Area Computer Architecture Workshop (BARC), Feb., 2006. | + | *<section begin=bjc4 /> B. Jiang and Y. Fei, "Traffic and Vehicle Speed Prediction with Neural Network and Hidden Markov Model in Vehicular Networks," Proc. IEEE Intelligent Vehicles Symp. (IV'15), June, 2015. <section end=bjc4 /> |
| - | *Y. Fei, L. Zhong, and N. K. Jha, “An energy-aware framework for coordinated dynamic software management in mobile computers,” in ACM/IEEE Int. Symp. on Modeling, Analysis, and Simulation of Computer & Telecommunication Systems (MASCOTS), Oct. 2004. | + | *<section begin=lzhc1 /> L. Zhang, A. A. Ding, Y. Fei, and P. Luo, “Efficient 2nd-order power analysis on masked devices utilizing multiple leakage,” Proc. IEEE Int. Symp. on Hardware Oriented Security & Trust (HOST), May 2015. <section end=lzhc1 /> |
| - | *Y. Fei, S. Ravi, A. Raghunathan, and N. K. Jha, “Energy-optimizing source code transformations for OS-driven embedded software,” in Proc. IEEE International Conference on VLSI Design, Jan. 2004. | + | *<section begin=yhc1 />Y. Han and Y. Fei, “A delay-aware probability-based MAC protocol for underwater acoustic sensor networks,” to appear, Proc. Int. Conf. on Computing, Networking and Communications, Wireless Ad Hoc and Sensor Networks Symposium (ICNC-WAHS), Feb. 2015. <section end=yhc1 /> |
| - | *W. Wang, T. K. Tan, J. Luo, Y. Fei, L. Shang, K. S. Vallerio, L. Zhong, A. Raghunathan, and N. K. Jha, “A comprehensive high-level synthesis system for control-flow intensive behaviors,” in Proc.IEEE Great Lakes Symposium on VLSI, April 2003. | + | *<section begin=plc1 />P. Luo, Y. Fei, X. Fang, A. A. Ding, M. Leeser, and D. R. Kaeli, “Power analysis attack on hardware implementation of MAC-Keccak on FPGAs,” Proc. Int. Conf. on Reconfigurable Computing and FPGAs (ReConfig’14), Dec. 2014. <section end=plc1 /> |
| - | *Y. Fei, S. Ravi, A. Raghunathan, and N. K. Jha, “Energy estimation for extensible processors,” in Proc. IEEE Design Automation & Test in Europe Conference, Mar. 2003. | + | *<section begin=plc2 />P. Luo, Y. Fei, L. Zhang, and A. A. Ding, “Side-channel power analysis of different protection schemes against fault attacks on AES,” Proc. Int. Conf. on Reconfigurable Computing and FPGAs (ReConfig’14), Dec. 2014. <section end=plc2 /> |
| - | *L. Zhong, J. Luo, Y. Fei, and N. K. Jha, “Register binding based power management for high-level synthesis of control-flow intensive behaviors,” in Proc. IEEE Int. Conf. Computer Design, Sept. 2002. | + | *<section begin=msc1 /> M. Shafaei and Y. Fei, "HiTS: A high-throughput memory scheduling scheme to mitigate denial-of-service attacks in multi-core systems" Int. Symp. on Computer Architecture and High Performance Computing (SPAC-PAD), Oct. 2014. <section end=msc1 /> |
| - | *Y. Fei and N. K. Jha, “Functional partitioning for low-power distributed systems of systems-on-a-chip,” in Proc. IEEE Asia South Pacific Design Automation Conference, Jan.2002. | + | *<section begin=adc1 /> A. A. Ding, L. Zhang, Y. Fei, and P. Luo "A statistical model for multivariate DPA on masked devices," Proc. Int. Wksp on Cryptographic Hardware & Embedded Systems (CHES), Sept. 2014. <section end=adc1 /> |
| + | *<section begin=tsc1 /> T. Swamy, N. Shah, P. Luo, Y. Fei, and D. Kaeli, "Scalable and efficient implementation of correlation power analysis using Graphic Processing Units (GPUs)," in Wkshp on Hardware and Architectural Support for Security & Privacy (HASP), in conjunction with Int. Symp. Computer Architecture, June 2014. <section end=tsc1 /> | ||
| + | *<section begin=bjc3 /> B. Jiang and Y. Fei, "On-road PHEV power management with hierarchical strategies in vehicular networks," Proc. IEEE Intelligent Vehicles Symp. (IV'14), June, 2014. <section end=bjc3 /> | ||
| + | *<section begin=thc6 /> T. Hu and Y. Fei, "An adaptive routing protocol based on connectivity prediction for underwater disruption tolerant networks," IEEE Global Communications Conf. (GlobeCom), Dec. 2013. <section end=thc6 /> | ||
| + | *<section begin=thc5 /> T. Hu and Y. Fei, "DSH-MAC: Medium Access Control Based on Decoupled and Suppressed Handshaking for Long-delay Underwater Acoustic Sensor Networks," IEEE Conf. on Local Computer Networks (LCN), Oct. 2013. <section end=thc5 /> | ||
| + | *<section begin=jcc5 /> J. C. Martinez Santos and Y. Fei, "Micro-architectural support for metadata coherence in multi-core dynamic information flow tracking," Int. Workshop on Hardware & Architectural Support for Security and Privacy (HASP), in Conjunction with Int. Symp. on Computer Architecture (ISCA), June 2013. <section end=jcc5 /> | ||
| + | *<section begin=bjc2 /> B. Jiang and Y. Fei, "Decentralized scheduling of PEV on-street parking and charging for smart grid reactive power compensation," Proc. IEEE PES Innovative Smart Grid Technologies (ISGT), Feb. 2013. <section end=bjc2 /> | ||
| + | *<section begin=jcc4 /> J. C. Martinez Santos and Y. Fei, "Designing and implementing a malicious 8051 processor,” Proc. IEEE Int. Symp. on Defect and Fault Tolerance in VLSI & Nanotechnology Systems, Special Session on Hardware Security Session on Capture the Chip, Oct. 2012.<section end=jcc4 /> | ||
| + | *<section begin=jcc3 />J. C. Martinez Santos, Y. Fei, and Z. J. Shi, “Static secure page allocation for light-weight dynamic information flow tracking,” Int. Conf. on Compilers, Architecture & Synthesis for Embedded Systems (CASES), Oct. 2012. <section end=jcc3 /> | ||
| + | *<section begin=yfc8 />Y. Fei, Q. Luo, and A. A. Ding, “A statistical model for DPA with novel algorithmic confusion analysis,” Proc. Int. Wksp on Cryptographic Hardware & Embedded Systems(CHES), Sept. 2012. <section end=yfc8 /> | ||
| + | *<section begin=thc4 />T. Hu and Y. Fei, “MURAO: A multi-level routing protocol for acoustic-optical hybrid underwater wireless sensor networks,” Proc. IEEE Communications Society Conf. on Sensor, Mesh, and Ad Hoc Communications and Networks (SECON), June, 2012. <section end=thc4 /> | ||
| + | *<section begin=xgc4 />X. Guan and Y. Fei, “Adaptive extended min-sum algorithm for nonbinary LDPC decoding, ” Proc. IEEE GLOBECOM, Dec. 2011. <section end=xgc4 /> | ||
| + | *<section begin=bjc1 />B. Jiang and Y. Fei, “Dynamic residential demand response and distributed generation management in smart microgrid with hierarchical agents,” Proc. Int. Conf. on Smart Grid & Clean Energy Technologies, Sept. 2011. <section end=bjc1 /> | ||
| + | *<section begin=qlc1 />Q. Luo and Y. Fei, “Algorithmic collision analysis of evaluating cryptographic systems and side-channel attacks,” Proc. IEEE Int. Symp. on Hardware Oriented Security & Trust (HOST), June 2011. <section end=qlc1 /> | ||
| + | *<section begin=thc2 />T. Hu and Y. Fei, “An adaptive and energy-efficient routing protocol based on machine learning for underwater delay tolerant networks,” ACM/IEEE Int. Symp. on Modeling, Analysis, and Simulation of Computer & Telecommunication Systems (MASCOTS), Aug. 2010. <section end=thc2 /> | ||
| + | *<section begin=hlc7 />H. Lin and Y. Fei, “Exploring custom instruction synthesis for application-specific instruction set processors with multiple design objectives,” IEEE Int. Symp. on Low Power Electronics & Design, Aug. 2010. <section end=hlc7 /> | ||
| + | *<section begin=hlc6 />H. Lin and Y. Fei, “A novel multi-objective instruction synthesis flow for application-specific instruction set processors,” ACM Proc. Great Lakes Symp. VLSI, May 2010. <section end=hlc6 /> | ||
| + | *<section begin=jcc2 />J. C. Martinez Santos, Y. Fei, and Z. J. Shi, “PIFT: Efficient dynamic information flow tracking using secure page allocation,” in WkShp on Embedded System Security (WESS) (held in conjunction with Embedded Systems Week), Oct. 2009. <section end=jcc2 /> | ||
| + | *<section begin=hlc5 />H. Lin and Y. Fei, “Resource sharing of pipelined custom hardware extension for energy-efficient application-specific instruction set processor,” in Proc. IEEE Int. Conf. Computer Design, Oct. 2009. <section end=hlc5 /> | ||
| + | *<section begin=xgc3 />X. Guan, Y. Fei, and H. Lin, “A hierarchical design of application-specific instruction set processors for high-throughput FFT,” in Proc. IEEE Int. Symp. on Circuits and Systems, May 2009. <section end=xgc3 /> | ||
| + | *<section begin=xgc2 />X. Guan, H. Lin, and Y. Fei, “Design of an application-specific instruction set processor for high-throughput and scalable FFT,” in Proc. IEEE Design Automation & Test in Europe Conf., Apr. 2009. <section end=xgc2 /> | ||
| + | *<section begin=hyc1 />H. Yan, Z. J. Shi, and Y. Fei, “Efficient implementation of Elliptic Curve Cryptography on DSP for underwater sensor networks,” WkShp on Optimizations for DSP & Embedded Systems (held in conjunction with IEEE/ACM Int. Symp. on Code Generation & Optimization), Mar. 2009. <section end=hyc1 /> | ||
| + | *<section begin=thc1 />T. Hu and Y. Fei, “QELAR - A Q-learning-based energy-efficient and lifetime-aware routing protocol for underwater sensor networks,” in IEEE Int. Performance Computing & Communications Conf., Dec. 2008. <section end=thc1 /> | ||
| + | *<section begin=jcc1 />J. C. Martinez Santos and Y. Fei, “Leveraging speculative architectures for run-time program validation,” in Proc. IEEE Int. Conf. Computer Design, Oct. 2008. <section end=jcc1 /> | ||
| + | *<section begin=vkc1 />V. Kundeti, Y. Fei, and Sanguthevar Rajasekaran, “An efficient digital circuit for implementing sequence alignment algorithm in an extended processor,” in IEEE Int. Conf. Application-specific Systems, Architectures & Processors, July 2008. <section end=vkc1 /> | ||
| + | *<section begin=xgc1 />X. Guan and Y. Fei, “Reducing power consumption of embedded processors through register file partitioning and compiler support,” in IEEE Int. Conf. Application-specific Systems, Architectures & Processors, July 2008. <section end=xgc1 /> | ||
| + | *<section begin=hlc4 />H. Lin, G. Sun. Y. Fei, Y. Xie, and A. Sivasubramaniam, “Thermal-aware design considerations for application-specific instruction set processor,” in IEEE Symp. on Application Specific Processors, June, 2008.<section end=hlc4 /> | ||
| + | *<section begin=hlc3 />H. Lin and Y. Fei, “Harnessing horizontal parallelism and vertical instruction packing of programs to improve system overall efficiency,” in Proc. IEEE Design Automation & Test in Europe Conf., Mar. 2008. <section end=hlc3 /> | ||
| + | *<section begin=hlc2 />H. Lin, X. Guan, Y. Fei, and Z. Shi, “Compiler-assisted architectural support for program code integrity monitoring in application-specific instruction set processors,” in IEEE Int. Conf. on Computer Design, Oct. 2007. <section end=hlc2 /> | ||
| + | *<section begin=yfc7 />Y. Fei, H. D. Lin, and X. Guan, “A hardware/software cooperative approach for reducing memory traffic in application-specific instruction set processors,” in IEEE Int. Midwest Symp. on Circuits & Systems, Aug. 2007. <section end=yfc7 /> | ||
| + | *<section begin=yfc6 />Y. Fei and Z. Shi, “Microarchitectural support for program code integrity monitoring in application-specific instruction set processors,” in Proc. IEEE Design Automation & Test in Europe Conf., Apr. 2007. <section end=yfc6 /> | ||
| + | *<section begin=hlc1 />H. Lin and Y. Fei, “Utilizing custom registers in application-specific instruction set processors for register spills elimination,” in Proc. ACM Great Lakes Symp. on VLSI, Mar. 2007. <section end=hlc1 /> | ||
| + | *<section begin=yfc5 />Y. Fei and Z. Shi, “Embedding program code integrity monitoring in application-specific instruction set processors,” in Annual Boston Area Computer Architecture Workshop (BARC), Jan. 2007. <section end=yfc5 /> | ||
| + | *<section begin=hdc1 />H. D. Lin and Y. Fei, “Custom register binding in application-specific instruction set processors to eliminate register spills,” in Annual Boston Area Computer Architecture Workshop (BARC), Jan. 2007. <section end=hdc1 /> | ||
| + | *<section begin=zsc1 />Z. Shi and Y. Fei, “Exploring architectural challenges in scalable underwater wireless sensor networks,” in Annual Boston Area Computer Architecture Workshop (BARC), Feb., 2006. <section end=zsc1 /> | ||
| + | *<section begin=yfc4 />Y. Fei, L. Zhong, and N. K. Jha, “An energy-aware framework for coordinated dynamic software management in mobile computers,” in ACM/IEEE Int. Symp. on Modeling, Analysis, and Simulation of Computer & Telecommunication Systems (MASCOTS), Oct. 2004.<section end=yfc4 /> | ||
| + | *<section begin=yfc3 />Y. Fei, S. Ravi, A. Raghunathan, and N. K. Jha, “Energy-optimizing source code transformations for OS-driven embedded software,” in Proc. IEEE International Conference on VLSI Design, Jan. 2004. <section end=yfc3 /> | ||
| + | *<section begin=wwc1 />W. Wang, T. K. Tan, J. Luo, Y. Fei, L. Shang, K. S. Vallerio, L. Zhong, A. Raghunathan, and N. K. Jha, “A comprehensive high-level synthesis system for control-flow intensive behaviors,” in Proc.IEEE Great Lakes Symposium on VLSI, April 2003. <section end=wwc1 /> | ||
| + | *<section begin=yfc2 />Y. Fei, S. Ravi, A. Raghunathan, and N. K. Jha, “Energy estimation for extensible processors,” in Proc. IEEE Design Automation & Test in Europe Conference, Mar. 2003. <section end=yfc2 /> | ||
| + | *<section begin=lzc1 />L. Zhong, J. Luo, Y. Fei, and N. K. Jha, “Register binding based power management for high-level synthesis of control-flow intensive behaviors,” in Proc. IEEE Int. Conf. Computer Design, Sept. 2002. <section end=lzc1 /> | ||
| + | *<section begin=yfc1 />Y. Fei and N. K. Jha, “Functional partitioning for low-power distributed systems of systems-on-a-chip,” in Proc. IEEE Asia South Pacific Design Automation Conference, Jan.2002. <section end=yfc1 /> | ||
Latest revision as of 15:04, 16 August 2018
Book Chapters
- Y. Fei, T. Eisenbarth, and D. Serpanos: Guest Editorial: Special Section on Embedded System Security. Embedded System Letters 7(1): 2015.
- Y. Fei and J. C. Martinez Santos, “Security in embedded systems,” In: M. Tehranipoor and C. Wang, Eds. Introduction to Hardware Security and Trust. New York: Springer, 2012.
Journal Papers
- C. Luo, Y. Fei, L. Zhang, A. A. Ding, P. Luo, S. Mukherjee, and D. Kaeli, “Power analysis attack of an AES GPU implementation,” Springer. J. Hardware & System Security (HASS), Vol. 2, No. 1, pp. 69-82, Mar. 2018.
- P. Luo, K. Athanasiou, Y. Fei, and T. Wahl, “Algebraic fault analysis of SHA-3 under relaxed fault models,” IEEE Trans. on Information Forensics and Security, Vol. 13, No. 7, July 2018.
- Y. Han and Y. Fei, “TARS: A traffic-adaptive receiver-synchronized medium access control protocol for underwater sensor networks”, ACM Trans. On Sensor Networks (TOSN), vol. 13(4), pp. 27:1-27:25, Dec. 2017.
- B. Jiang and Y. Fei, “A PHEV power management cyber-physical system for on-road applications,” IEEE Trans. On Vehicular Technology (TVT), vol. 66, no. 7, pp. 5797-6807, July 2017.
- B. Jiang and Y. Fei, “Vehicle speed prediction by two-level data driven models in vehicular networks,” IEEE Trans. Intelligent Transportation Systems, vol. 18, no. 7, pp. 1793-1801, July 2017.
- P. Luo, Y. Fei, L. Zhang, and A. A. Ding, “Differential fault analysis of SHA-3 under relaxed fault models,” Springer. J. Hardware & System Security (HASS), vol. 1, no. 2, pp. 156-172, June 2017.
- Y. Han and Y. Fei, “DAP-MAC: A delay-aware probability-based MAC protocol for underwater acoustic sensor networks,"Elsevier Ad Hoc Networks (ADHOC), vol. 48, pp.80-92, Sept. 2016.
- Y. Fei, A. Ding, J. Lao, and L. Zhang, “A statistics-based success rate model for DPA and CPA,"Journal of Cryptographic Engineering, vol. 5, no.4, pp.227-243, Nov. 2015.
- B. Jiang and Y. Fei, “Smart home in smart microgrid: A cost-effective energy ecosystem with intelligent hierarchical agents,”IEEE Trans. on Smart Grid, vol. 6, no.1, pp.3-13, Jan. 2015.
- A. A. Ding, L. Zhang, Y. Fei, and P. Luo, “A statistical model for higher order DPA on masked devices,” IACR ePrint, 2014/433. (https://eprint.iacr.org/2014/433.pdf).
- Y. Fei, A. A. Ding, J. Lao and L. Zhang, “A statistics-based fundamental model for side-channel attack analysis,” IACR ePrint, 2014/152. (https://eprint.iacr.org/2014/152.pdf).
- J. C. Martinez Santos and Y. Fei, “Leveraging speculative architectures for run-time program validation,” ACM Trans. on Embedded Computing Systems, vol. 13, no.1, Aug. 2013.
- H. Lin and Y. Fei, “Resource sharing of pipelined custom hardware extension for energy-efficient application-specific instruction set processor design,” ACM Trans. on Design Automation of Electronic Systems, vol. 17, no.4, Oct. 2012.
- H. Lin, T. Hu, and Y. Fei, “Utilizing custom registers in application-specific instruciton set processors for register spill elimination,” ACM Trans. on Design Automation of Electronic Systems, vol. 17, no.4, Oct. 2012.
- X. Guan, Y. Fei, and H. Lin, “Hierarchical design of an application-specific instruction set processor for high-throughput and scalable FFT processing,” IEEE Trans. on VLSI, vol. 20, no.3, pp. 551-563, Mar. 2012.
- H. Lin, Y. Fei, X. Guan, and Z. J. Shi, “Architectural enhancement and system software support for program code integrity monitoring in application-specific instruction set processors,” IEEE Trans. on VLSI,vol. 18, no. 11, pp. 1319 - 1332, Nov. 2010.
- X. Guan and Y. Fei, “Register file partitioning and compiler support for reducing power consumption in embedded processors,” IEEE Trans. on VLSI, vol. 18, no. 8, pp. 1248 - 1252, Aug. 2010.
- T. Hu and Y. Fei, “QELAR: A machine-learning-based adaptive routing protocol for energy efficient and lifetime-extended underwater sensor networks,” IEEE Trans. on Mobile Computing, vol. 9, no. 6, June 2010.
- X. Guan and Y. Fei, “Register file partitioning and re-compilation for register file power reduction,” ACM Trans. on Design Automation of Electronic Systems, vol. 15, no. 3, May 2010.
- H. Lin and Y. Fei, “Orchestrating horizontal parallelism and vertical instruction packing of programs to improve system overall efficiency,” IEEE Trans. on Computers, vol. 58, no. 9, pp. 1211-1220, Sept. 2009.
- Y. Fei, L. Zhong, and N. K. Jha, “An energy-aware framework for dynamic software management in mobile computing systems,” ACM Trans. on Embedded Computing Systems, vol. 7, no. 3, Apr. 2008.
- Y. Fei, S. Ravi, A. Raghunathan, and N. K. Jha, “Energy-optimizing source code transformations for operating system driven embedded software,” ACM Trans. on Embedded Computing Systems, vol. 7, no. 1, Dec. 2007.
- Y. Fei and N. K. Jha, “Integrated functional partitioning and synthesis for low power distributed systems of systems-on-a-chip,” invited paper, Special Issue on Hardware-software Codesign for SOC in Int. Journal Embedded Systems, Vol.1, Nos.1/2, pp.2-13, 2005.
- J. Luo, L. Zhong, Y. Fei, and N. K. Jha, “Register binding based RTL power management for control-flow intensive designs,” IEEE Trans. on Computer-aided Design of Integrated Circuits and Systems, vol. 23, no. 8, Aug. 2004.
- Y. Fei, S. Ravi, A. Raghunathan, and N. K. Jha, “A hybrid energy estimation technique for extensible processors,” IEEE Trans. on Computer-aided Design of Integrated Circuits and Systems, vol. 23, no. 5, pp. 652-664, May 2004.
- Y. Fei, X. Zheng, H. Zhang, Y. Guo, and B. Zhou, “A novel scheme of power equalization and power management in WDM all-optical networks,” IEEE Photon. Technol. Lett., vol. 11, no. 9, pp.1189-1191, Sept.1999.
Conferences and Workshops Papers
- E. Karimi, Z.H. Jiang, D. Kaeli, and Y. Fei, “A timing side-channel attack on a mobile GPU,” IEEE Int. Conf. Computer Design (ICCD), Oct. 2018
- M. Sabbagh, Y. Fei, T. Wahl, and A. Ding, “SCADET: A side-channel attack detection tool for tracking Prime+Probe,” ACM Int. Conf. Computer-aided Design (ICCAD), Nov. 2018.
- C. Luo, Y. Fei, and D. Kaeli, “Effective simple-power analysis attacks of Elliptic Curve Cryptography on embedded systems,” ACM Int. Conf. Computer-aided Design (ICCAD), Nov. 2018.
- C. Luo, Y. Fei, and D. Kaeli, “GPU acceleration of RSA is vulnerable to side-channel timing attacks,” ACM Int. Conf. Computer-aided Design (ICCAD), Nov. 2018.
- A. Adam Ding, L. Zhang, F. Durvaux, F-X. Standaert, and Y. Fei, “Toward sound and optimal leakage detection procedure,” Smart Card Research and Advanced Application Conference (CARDIS), Nov. 2017.
- Z. Jiang and Y. Fei, “A novel cache bank timing attack”, ACM Int. Conf. Computer-Aided Design (ICCAD), Nov. 2017.
- Pei Luo, Konstantinos Anthansiou, Liwei Zhang, Zhen Jiang, Yunsi Fei, A. Adam Ding and Thomas Wahl, “A First Step Towards Automatic Compiler Assisted Threshold Implementation Design,” IEEE Int. Conf. on Computer Design (ICCD), Nov. 2017.
- Z. Jiang, Y. Fei, and D. R. Kaeli, “A novel side-channel timing attack on GPUs,” Great Lake Symp. on VLSI (GLSVLSI), May 2017.
- C. Luo, Y. Fei, and A. Ding, “Side-channel power analysis of XTS-AES,” Proc. Design Automation & Test in Europe (DATE), Mar. 2017.
- P. Luo, K. Athanasiou, Y. Fei, and T. Wahl, “Algebraic fault analysis of SHA-3,” Proc. Design Automation & Test in Europe (DATE), Mar. 2017.
- Y. M. Aval, Y. Han, A. Tu, S. Basagni, M. Stojanovic, and Y. Fei, “Testbed-based performance evaluation of handshake-free MAC protocols for underwater acoustic sensor networks,” MTS/IEEE Proc. Oceans, Sept. 2016.
- P. Luo, Y. Fei, L. Zhang, and A. A. Ding, “Differential fault analysis of SHA3-224 and SHA3-256,” Int. WkShp on Fault Diagnosis and Tolerance in Cryptography (FDTC), Aug. 2016.
- Y. Han, Y. Fei, and A. A. Ding, “A stochastic MAC protocol with randomized power control for underwater sensor networks,” IEEE Int. Conf. on Sensing, Communication and Networking (SECON), June 2016.
- P. Luo, C. Li, and Y. Fei, “Concurrent error detection for reliable SHA-3 design,” Great Lake Symp. on VLSI (GLSVLSI), May 2016.
- Z. Jiang, Y. Fei, and D. R. Kaeli, “A complete key recovery timing attack on a GPU,” Int. Symp. High Performance Computer Architecture (HPCA), Mar. 2016.
- L. Zhang, A. A. Ding, Y. Fei, and P. Luo, “A Unified Metric for Quantifying Information Leakage of Cryptographic Devices under Power Analysis Attacks,” Int. Conf. on the Theory and Application of Cryptology and Information Security (AsiaCrypt), Nov.-Dec. 2015.
- C. Luo, Y. Fei, P. Luo, S. Mukherjee, and D. Kaeli, “Side-channel power analysis of a GPU AES implementation,” Int. Conf. Computer Design (ICCD), Oct. 2015.
- Y. Han and Y. Fei, “TARS: A Traffic-Adaptive Receiver-Synchronized MAC Protocol for Underwater Sensor Networks,” Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), Best Paper Award, Oct. 2015.
- P. Luo, L. Zhang, Y. Fei, and A. A. Ding "Towards Secure Cryptographic Software Implementation Against Side-Channel Power Analysis Attacks", Int. Conf. on Application-specific Systems, Architectures, and Processors (ASAP), July 2015.
- X. Fang, Y. Fei, and M. Leeser, "Balance Power Leakage to Fight Against Side-Channel Analysis at Gate Level in FPGAs", Int. Conf. on Application-specific Systems, Architectures, and Processors (ASAP), July 2015.
- P. Luo, Y. Fei, X. Fang, A. Adam Ding, D. R. Kaeli, and M. Leeser, “Side-channel analysis of MAC-Keccak hardware implementations,” in Wkshp on Hardware and Architectural Support for Security & Privacy (HASP), in conjunction with Int. Symp. Computer Architecture, June 2015.
- B. Jiang and Y. Fei, "Traffic and Vehicle Speed Prediction with Neural Network and Hidden Markov Model in Vehicular Networks," Proc. IEEE Intelligent Vehicles Symp. (IV'15), June, 2015.
- L. Zhang, A. A. Ding, Y. Fei, and P. Luo, “Efficient 2nd-order power analysis on masked devices utilizing multiple leakage,” Proc. IEEE Int. Symp. on Hardware Oriented Security & Trust (HOST), May 2015.
- Y. Han and Y. Fei, “A delay-aware probability-based MAC protocol for underwater acoustic sensor networks,” to appear, Proc. Int. Conf. on Computing, Networking and Communications, Wireless Ad Hoc and Sensor Networks Symposium (ICNC-WAHS), Feb. 2015.
- P. Luo, Y. Fei, X. Fang, A. A. Ding, M. Leeser, and D. R. Kaeli, “Power analysis attack on hardware implementation of MAC-Keccak on FPGAs,” Proc. Int. Conf. on Reconfigurable Computing and FPGAs (ReConfig’14), Dec. 2014.
- P. Luo, Y. Fei, L. Zhang, and A. A. Ding, “Side-channel power analysis of different protection schemes against fault attacks on AES,” Proc. Int. Conf. on Reconfigurable Computing and FPGAs (ReConfig’14), Dec. 2014.
- M. Shafaei and Y. Fei, "HiTS: A high-throughput memory scheduling scheme to mitigate denial-of-service attacks in multi-core systems" Int. Symp. on Computer Architecture and High Performance Computing (SPAC-PAD), Oct. 2014.
- A. A. Ding, L. Zhang, Y. Fei, and P. Luo "A statistical model for multivariate DPA on masked devices," Proc. Int. Wksp on Cryptographic Hardware & Embedded Systems (CHES), Sept. 2014.
- T. Swamy, N. Shah, P. Luo, Y. Fei, and D. Kaeli, "Scalable and efficient implementation of correlation power analysis using Graphic Processing Units (GPUs)," in Wkshp on Hardware and Architectural Support for Security & Privacy (HASP), in conjunction with Int. Symp. Computer Architecture, June 2014.
- B. Jiang and Y. Fei, "On-road PHEV power management with hierarchical strategies in vehicular networks," Proc. IEEE Intelligent Vehicles Symp. (IV'14), June, 2014.
- T. Hu and Y. Fei, "An adaptive routing protocol based on connectivity prediction for underwater disruption tolerant networks," IEEE Global Communications Conf. (GlobeCom), Dec. 2013.
- T. Hu and Y. Fei, "DSH-MAC: Medium Access Control Based on Decoupled and Suppressed Handshaking for Long-delay Underwater Acoustic Sensor Networks," IEEE Conf. on Local Computer Networks (LCN), Oct. 2013.
- J. C. Martinez Santos and Y. Fei, "Micro-architectural support for metadata coherence in multi-core dynamic information flow tracking," Int. Workshop on Hardware & Architectural Support for Security and Privacy (HASP), in Conjunction with Int. Symp. on Computer Architecture (ISCA), June 2013.
- B. Jiang and Y. Fei, "Decentralized scheduling of PEV on-street parking and charging for smart grid reactive power compensation," Proc. IEEE PES Innovative Smart Grid Technologies (ISGT), Feb. 2013.
- J. C. Martinez Santos and Y. Fei, "Designing and implementing a malicious 8051 processor,” Proc. IEEE Int. Symp. on Defect and Fault Tolerance in VLSI & Nanotechnology Systems, Special Session on Hardware Security Session on Capture the Chip, Oct. 2012.
- J. C. Martinez Santos, Y. Fei, and Z. J. Shi, “Static secure page allocation for light-weight dynamic information flow tracking,” Int. Conf. on Compilers, Architecture & Synthesis for Embedded Systems (CASES), Oct. 2012.
- Y. Fei, Q. Luo, and A. A. Ding, “A statistical model for DPA with novel algorithmic confusion analysis,” Proc. Int. Wksp on Cryptographic Hardware & Embedded Systems(CHES), Sept. 2012.
- T. Hu and Y. Fei, “MURAO: A multi-level routing protocol for acoustic-optical hybrid underwater wireless sensor networks,” Proc. IEEE Communications Society Conf. on Sensor, Mesh, and Ad Hoc Communications and Networks (SECON), June, 2012.
- X. Guan and Y. Fei, “Adaptive extended min-sum algorithm for nonbinary LDPC decoding, ” Proc. IEEE GLOBECOM, Dec. 2011.
- B. Jiang and Y. Fei, “Dynamic residential demand response and distributed generation management in smart microgrid with hierarchical agents,” Proc. Int. Conf. on Smart Grid & Clean Energy Technologies, Sept. 2011.
- Q. Luo and Y. Fei, “Algorithmic collision analysis of evaluating cryptographic systems and side-channel attacks,” Proc. IEEE Int. Symp. on Hardware Oriented Security & Trust (HOST), June 2011.
- T. Hu and Y. Fei, “An adaptive and energy-efficient routing protocol based on machine learning for underwater delay tolerant networks,” ACM/IEEE Int. Symp. on Modeling, Analysis, and Simulation of Computer & Telecommunication Systems (MASCOTS), Aug. 2010.
- H. Lin and Y. Fei, “Exploring custom instruction synthesis for application-specific instruction set processors with multiple design objectives,” IEEE Int. Symp. on Low Power Electronics & Design, Aug. 2010.
- H. Lin and Y. Fei, “A novel multi-objective instruction synthesis flow for application-specific instruction set processors,” ACM Proc. Great Lakes Symp. VLSI, May 2010.
- J. C. Martinez Santos, Y. Fei, and Z. J. Shi, “PIFT: Efficient dynamic information flow tracking using secure page allocation,” in WkShp on Embedded System Security (WESS) (held in conjunction with Embedded Systems Week), Oct. 2009.
- H. Lin and Y. Fei, “Resource sharing of pipelined custom hardware extension for energy-efficient application-specific instruction set processor,” in Proc. IEEE Int. Conf. Computer Design, Oct. 2009.
- X. Guan, Y. Fei, and H. Lin, “A hierarchical design of application-specific instruction set processors for high-throughput FFT,” in Proc. IEEE Int. Symp. on Circuits and Systems, May 2009.
- X. Guan, H. Lin, and Y. Fei, “Design of an application-specific instruction set processor for high-throughput and scalable FFT,” in Proc. IEEE Design Automation & Test in Europe Conf., Apr. 2009.
- H. Yan, Z. J. Shi, and Y. Fei, “Efficient implementation of Elliptic Curve Cryptography on DSP for underwater sensor networks,” WkShp on Optimizations for DSP & Embedded Systems (held in conjunction with IEEE/ACM Int. Symp. on Code Generation & Optimization), Mar. 2009.
- T. Hu and Y. Fei, “QELAR - A Q-learning-based energy-efficient and lifetime-aware routing protocol for underwater sensor networks,” in IEEE Int. Performance Computing & Communications Conf., Dec. 2008.
- J. C. Martinez Santos and Y. Fei, “Leveraging speculative architectures for run-time program validation,” in Proc. IEEE Int. Conf. Computer Design, Oct. 2008.
- V. Kundeti, Y. Fei, and Sanguthevar Rajasekaran, “An efficient digital circuit for implementing sequence alignment algorithm in an extended processor,” in IEEE Int. Conf. Application-specific Systems, Architectures & Processors, July 2008.
- X. Guan and Y. Fei, “Reducing power consumption of embedded processors through register file partitioning and compiler support,” in IEEE Int. Conf. Application-specific Systems, Architectures & Processors, July 2008.
- H. Lin, G. Sun. Y. Fei, Y. Xie, and A. Sivasubramaniam, “Thermal-aware design considerations for application-specific instruction set processor,” in IEEE Symp. on Application Specific Processors, June, 2008.
- H. Lin and Y. Fei, “Harnessing horizontal parallelism and vertical instruction packing of programs to improve system overall efficiency,” in Proc. IEEE Design Automation & Test in Europe Conf., Mar. 2008.
- H. Lin, X. Guan, Y. Fei, and Z. Shi, “Compiler-assisted architectural support for program code integrity monitoring in application-specific instruction set processors,” in IEEE Int. Conf. on Computer Design, Oct. 2007.
- Y. Fei, H. D. Lin, and X. Guan, “A hardware/software cooperative approach for reducing memory traffic in application-specific instruction set processors,” in IEEE Int. Midwest Symp. on Circuits & Systems, Aug. 2007.
- Y. Fei and Z. Shi, “Microarchitectural support for program code integrity monitoring in application-specific instruction set processors,” in Proc. IEEE Design Automation & Test in Europe Conf., Apr. 2007.
- H. Lin and Y. Fei, “Utilizing custom registers in application-specific instruction set processors for register spills elimination,” in Proc. ACM Great Lakes Symp. on VLSI, Mar. 2007.
- Y. Fei and Z. Shi, “Embedding program code integrity monitoring in application-specific instruction set processors,” in Annual Boston Area Computer Architecture Workshop (BARC), Jan. 2007.
- H. D. Lin and Y. Fei, “Custom register binding in application-specific instruction set processors to eliminate register spills,” in Annual Boston Area Computer Architecture Workshop (BARC), Jan. 2007.
- Z. Shi and Y. Fei, “Exploring architectural challenges in scalable underwater wireless sensor networks,” in Annual Boston Area Computer Architecture Workshop (BARC), Feb., 2006.
- Y. Fei, L. Zhong, and N. K. Jha, “An energy-aware framework for coordinated dynamic software management in mobile computers,” in ACM/IEEE Int. Symp. on Modeling, Analysis, and Simulation of Computer & Telecommunication Systems (MASCOTS), Oct. 2004.
- Y. Fei, S. Ravi, A. Raghunathan, and N. K. Jha, “Energy-optimizing source code transformations for OS-driven embedded software,” in Proc. IEEE International Conference on VLSI Design, Jan. 2004.
- W. Wang, T. K. Tan, J. Luo, Y. Fei, L. Shang, K. S. Vallerio, L. Zhong, A. Raghunathan, and N. K. Jha, “A comprehensive high-level synthesis system for control-flow intensive behaviors,” in Proc.IEEE Great Lakes Symposium on VLSI, April 2003.
- Y. Fei, S. Ravi, A. Raghunathan, and N. K. Jha, “Energy estimation for extensible processors,” in Proc. IEEE Design Automation & Test in Europe Conference, Mar. 2003.
- L. Zhong, J. Luo, Y. Fei, and N. K. Jha, “Register binding based power management for high-level synthesis of control-flow intensive behaviors,” in Proc. IEEE Int. Conf. Computer Design, Sept. 2002.
- Y. Fei and N. K. Jha, “Functional partitioning for low-power distributed systems of systems-on-a-chip,” in Proc. IEEE Asia South Pacific Design Automation Conference, Jan.2002.
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