http://nueess.coe.neu.edu/nueess/index.php?feed=atom&target=Jcmartinez&title=Special%3AContributions 2026-05-15T05:04:06Z From NUEESS MediaWiki 1.15.5-7 http://nueess.coe.neu.edu/nueess/index.php/Juan_Carlos_Martinez_Santos 2013-07-05T14:39:17Z

<p>Jcmartinez:&#32;</p> <hr /> <div>[[image:Juan-photo.jpg|thumb|200px|left]]<br /> '''Juan Carlos Martinez Santos'''<br /> <br /> Ph.D Candidate<br /> <br /> Department of Electrical and Computer Engineering<br /> <br /> Northeastern University<br /> <br /> Egan 235<br /> <br /> Boston, MA 02115, USA<br /> <br /> Email: martinezsantos.j AT husky.neu.edu<br /> <br /> Webpage: http://laurel.engr.uconn.edu/~jcmartin<br /> <br /> == Education ==<br /> *Ph.D. Candidate: [http://www.ece.neu.edu/ece Dept. of Electrical and Computer Engineering], [http://www.northeastern.edu/ Northeastern University], USA, 2013 (expected)<br /> :Advisor: [http://www.ece.neu.edu/ece/index.php/component/content/170?task=view Prof. Yunsi Fei]<br /> <br /> *M.Sc and B.S.: [http://www.uis.edu.co/webUIS/es/academia/facultades/fisicoMecanicas/escuelas/e3t/ Escuela de Ingenierias Electrica, Electronica y Telecomunicaciones], [http://www.uis.edu.co/webUIS/en/index.html Universidad Industrial de Santander], Bucaramanga, Santander - Colombia, 2004 - 2001<br /> :Advisor: Prof. Jorge Ramon<br /> <br /> == Research ==<br /> *[[DIFT for multi-thread applications on multi-core architectures]]<br /> *[[Dynamic Information Flow Tracking]]<br /> *[[Anomalous Path Detection]]<br /> <br /> == Publications ==<br /> '' Journal Papers''<br /> *J. C. Martinez Santos, S. H. Contreras Ortiz, “Tele-operated Laboratory for Digital Systems Design” (Original Title: Laboratorio Tele-operado de Técnicas Digitales), in Revista Colombiana De Tecnologías De Avanzada, ISSN: 1692-7257 ed: Java Eu v.6 fasc. p.92 – 96. Colombia, 2005 – Language: Spanish<br /> *J. C. Martinez Santos, J. H. Ramon Suarez, “Teaching Digital Systems Design using Hardware Description Languages” (Original Title: Enseñanza de Sistemas Digitales usando lenguajes de descripción de hardware), in UIS Ingenierías ISSN: 1657-4583 ed: Publicaciones UIS v.2 fasc.1 p.35 – 39. Colombia ,2003 – Language: Spanish<br /> <br /> '' Conference Papers ''<br /> *J. C. Martinez Santos, Y. Fei, and Z. J. Shi, “PIFT: Efficient dynamic information flow tracking using secure page allocation,” in WkShp on Embedded System Security (WESS) (held in conjunction with Embedded Systems Week), Oct. 2009.<br /> *J. C. Martinez Santos and Y. Fei, “Leveraging speculative architectures for run-time program validation,” in Proc. IEEE Int. Conf. Computer Design, Oct. 2008.<br /> *J. C. Martinez Santos, L. S. Silva Lopez, “A Platform for Developing Skills on Implementation of Wireless Sensor Networks Using Active Learning”, in Active Learning on Engineering, Universidad de Los Andes, p.205 - 206, Bogota, Colombia, 2008<br /> *J. C. Martinez Santos, L. S. Silva Lopez, O. G. Erazo Cruz, “A Study Case: a WSN using IEE and MAC SMAC hardware with adjustable duty cycle for improving battery life time” (Original Title: El caso de una WSN empleando Hardware IEE y MAC SMAC, con variación de ciclos de trabajo para mejorar vida de Baterías), in Proc. i2ComM . ISBN: 9789588375 ed: I2COMM, p.122 - 127, Colombia 2008 – Language: Spanish<br /> *J. C. Martinez Santos, L. S. Silva Lopez, E. Ospina Mateus, “Analysis of a WSN inside of a car using the IEEE 802.15.4 standard with adjustable duty cycle for improving battery life time” (Original Title: Análisis de una WSN en un Automóvil bajo IEEE 802.15.4 con Variación de Ciclos de Trabajo para Mejorar Vida de Baterías), in IEEE Colcom 2007, Congreso Colombiano De Comunicaciones . ISBN: 978-958-44, Colombia, 2007 – Language: Spanish<br /> *J. C. Martinez Santos, S. H. Contreras Ortiz, E. Gomez Vasquez, O. Acevedo Patiño, “LABTO: Teleoperated Laboratory of Digital Systems Design” (Original Title: LABTO: Laboratorio TeleOperado de Tecnicas Digitales), in IEEE Colombian Workshop on Circuits and Systems , ISBN: 978-958-69 ed: Universidad De Los Andes. Colombia, 2006 – Language: Spanish<br /> *J. C. Martinez Santos, O. S. Bayter Fontalvo, “Total Harmonic Distortion meter using a Digital Signal Processor” (Original Title: Medidor de Distorsión Armónica Total basado en un Procesador Digital de Señales), in XI Simposio de Tratamiento de Señales, Imagenes y vision Artificial. . ISBN: 958-683-93 ed: Sociedad Colombiana de Tratamiento de Señales , v. I. Colombia, 2006 – Language: Spanish<br /> *J. C. Martinez Santos, S. H. Contreras Ortiz, E. Gomez Vasquez, O. Acevedo Patiño, “Tele-operated laboratory of Digital systems Desing” (Original Title: Laboratorio Tele-operado de Técnicas Digitales), in XXIV Reunión Nacional de Facultades de Ingeniería. ISBN: 958-608-049-8, p.195 – 199. Colombia, 2004 – Language: Spanish<br /> <br /> '' Books ''<br /> *J. C. Martinez Santos, J. Duque, “A text book for Digital Circuits” (Original Title: Circuitos Digitales). ed: Ediciones Tecnologica de Bolivar ISBN: 9589745946 v. 1 pages. 143. Colombia, 2004 – Language: Spanish</div>

Jcmartinez http://nueess.coe.neu.edu/nueess/index.php/File:UtbSignature.png 2013-02-07T13:30:26Z

<p>Jcmartinez:&#32;UTB signature</p> <hr /> <div>UTB signature</div>

Jcmartinez http://nueess.coe.neu.edu/nueess/index.php/File:Pift-architecture.png 2012-03-28T18:52:20Z

<p>Jcmartinez:&#32;</p> <hr /> <div></div>

Jcmartinez http://nueess.coe.neu.edu/nueess/index.php/File:Pift-idea.png 2012-03-28T18:51:56Z

<p>Jcmartinez:&#32;</p> <hr /> <div></div>

Jcmartinez http://nueess.coe.neu.edu/nueess/index.php/Dynamic_Information_Flow_Tracking 2012-03-28T18:51:35Z

<p>Jcmartinez:&#32;/* The General Idea */</p> <hr /> <div>== Abstract ==<br /> <br /> Dynamic information flow tracking (DIFT) is an effective security countermeasure for both low-level memory corruptions and high-level semantic attacks. However, many software approaches suffer large performance degradation, and hardware approaches have high logic and storage overhead. In this paper, we propose a flexible and light-weight hardware/software co-design approach to perform DIFT based on secure page allocation. Instead of associating every data with a taint tag, we aggregate data according to their taints, i.e., putting data with different attributes in separate memory pages. Our approach is a compiler-aided process with architecture support. The implementation and analysis show that the memory overhead is little, and our approach can protect critical information, including return address, indirect jump address, and system call IDs, from being overwritten by malicious users.<br /> <br /> <br /> == The General Idea ==<br /> [[File:pift-idea.png |thumb|right|350px|Virtual adreess space and page table on PIFT]]<br /> <br /> == The Architectural Design ==<br /> [[File:pift-architecture.png |thumb|right|350px|Architecture design]]<br /> <br /> == People ==<br /> <br /> * [[ Juan Carlos Martinez Santos]]<br /> <br /> == Publications ==<br /> <br /> *J. C. Martinez Santos, Y. Fei, and Z. J. Shi, “PIFT: Efficient dynamic information flow tracking using secure page allocation,” in WkShp on Embedded System Security (WESS) (held in conjunction with Embedded Systems Week), Oct. 2009.</div>

Jcmartinez http://nueess.coe.neu.edu/nueess/index.php/Dynamic_Information_Flow_Tracking 2012-03-28T18:51:08Z

<p>Jcmartinez:&#32;/* The General Idea */</p> <hr /> <div>== Abstract ==<br /> <br /> Dynamic information flow tracking (DIFT) is an effective security countermeasure for both low-level memory corruptions and high-level semantic attacks. However, many software approaches suffer large performance degradation, and hardware approaches have high logic and storage overhead. In this paper, we propose a flexible and light-weight hardware/software co-design approach to perform DIFT based on secure page allocation. Instead of associating every data with a taint tag, we aggregate data according to their taints, i.e., putting data with different attributes in separate memory pages. Our approach is a compiler-aided process with architecture support. The implementation and analysis show that the memory overhead is little, and our approach can protect critical information, including return address, indirect jump address, and system call IDs, from being overwritten by malicious users.<br /> <br /> <br /> == The General Idea ==<br /> [[File:pift-idea.png |thumb|right|350px|The architecture support in processor pipeline for control flow validation]]<br /> <br /> == The Architectural Design ==<br /> [[File:pift-architecture.png |thumb|right|350px|Architecture design]]<br /> <br /> == People ==<br /> <br /> * [[ Juan Carlos Martinez Santos]]<br /> <br /> == Publications ==<br /> <br /> *J. C. Martinez Santos, Y. Fei, and Z. J. Shi, “PIFT: Efficient dynamic information flow tracking using secure page allocation,” in WkShp on Embedded System Security (WESS) (held in conjunction with Embedded Systems Week), Oct. 2009.</div>

Jcmartinez http://nueess.coe.neu.edu/nueess/index.php/Dynamic_Information_Flow_Tracking 2012-03-28T18:50:25Z

<p>Jcmartinez:&#32;/* The Architectural Design */</p> <hr /> <div>== Abstract ==<br /> <br /> Dynamic information flow tracking (DIFT) is an effective security countermeasure for both low-level memory corruptions and high-level semantic attacks. However, many software approaches suffer large performance degradation, and hardware approaches have high logic and storage overhead. In this paper, we propose a flexible and light-weight hardware/software co-design approach to perform DIFT based on secure page allocation. Instead of associating every data with a taint tag, we aggregate data according to their taints, i.e., putting data with different attributes in separate memory pages. Our approach is a compiler-aided process with architecture support. The implementation and analysis show that the memory overhead is little, and our approach can protect critical information, including return address, indirect jump address, and system call IDs, from being overwritten by malicious users.<br /> <br /> <br /> == The General Idea ==<br /> [[File:architecture.png |thumb|right|350px|The architecture support in processor pipeline for control flow validation]]<br /> <br /> == The Architectural Design ==<br /> [[File:pift-architecture.png |thumb|right|350px|Architecture design]]<br /> <br /> == People ==<br /> <br /> * [[ Juan Carlos Martinez Santos]]<br /> <br /> == Publications ==<br /> <br /> *J. C. Martinez Santos, Y. Fei, and Z. J. Shi, “PIFT: Efficient dynamic information flow tracking using secure page allocation,” in WkShp on Embedded System Security (WESS) (held in conjunction with Embedded Systems Week), Oct. 2009.</div>

Jcmartinez http://nueess.coe.neu.edu/nueess/index.php/Dynamic_Information_Flow_Tracking 2012-03-28T18:49:44Z

<p>Jcmartinez:&#32;/* The General Idea */</p> <hr /> <div>== Abstract ==<br /> <br /> Dynamic information flow tracking (DIFT) is an effective security countermeasure for both low-level memory corruptions and high-level semantic attacks. However, many software approaches suffer large performance degradation, and hardware approaches have high logic and storage overhead. In this paper, we propose a flexible and light-weight hardware/software co-design approach to perform DIFT based on secure page allocation. Instead of associating every data with a taint tag, we aggregate data according to their taints, i.e., putting data with different attributes in separate memory pages. Our approach is a compiler-aided process with architecture support. The implementation and analysis show that the memory overhead is little, and our approach can protect critical information, including return address, indirect jump address, and system call IDs, from being overwritten by malicious users.<br /> <br /> <br /> == The General Idea ==<br /> [[File:architecture.png |thumb|right|350px|The architecture support in processor pipeline for control flow validation]]<br /> <br /> == The Architectural Design ==<br /> <br /> == People ==<br /> <br /> * [[ Juan Carlos Martinez Santos]]<br /> <br /> == Publications ==<br /> <br /> *J. C. Martinez Santos, Y. Fei, and Z. J. Shi, “PIFT: Efficient dynamic information flow tracking using secure page allocation,” in WkShp on Embedded System Security (WESS) (held in conjunction with Embedded Systems Week), Oct. 2009.</div>

Jcmartinez http://nueess.coe.neu.edu/nueess/index.php/Dynamic_Information_Flow_Tracking 2012-03-28T18:48:58Z

<p>Jcmartinez:&#32;/* Publications */</p> <hr /> <div>== Abstract ==<br /> <br /> Dynamic information flow tracking (DIFT) is an effective security countermeasure for both low-level memory corruptions and high-level semantic attacks. However, many software approaches suffer large performance degradation, and hardware approaches have high logic and storage overhead. In this paper, we propose a flexible and light-weight hardware/software co-design approach to perform DIFT based on secure page allocation. Instead of associating every data with a taint tag, we aggregate data according to their taints, i.e., putting data with different attributes in separate memory pages. Our approach is a compiler-aided process with architecture support. The implementation and analysis show that the memory overhead is little, and our approach can protect critical information, including return address, indirect jump address, and system call IDs, from being overwritten by malicious users.<br /> <br /> <br /> == The General Idea ==<br /> <br /> == The Architectural Design ==<br /> <br /> == People ==<br /> <br /> * [[ Juan Carlos Martinez Santos]]<br /> <br /> == Publications ==<br /> <br /> *J. C. Martinez Santos, Y. Fei, and Z. J. Shi, “PIFT: Efficient dynamic information flow tracking using secure page allocation,” in WkShp on Embedded System Security (WESS) (held in conjunction with Embedded Systems Week), Oct. 2009.</div>

Jcmartinez http://nueess.coe.neu.edu/nueess/index.php/Dynamic_Information_Flow_Tracking 2012-03-28T18:48:15Z

<p>Jcmartinez:&#32;/* Abstract */</p> <hr /> <div>== Abstract ==<br /> <br /> Dynamic information flow tracking (DIFT) is an effective security countermeasure for both low-level memory corruptions and high-level semantic attacks. However, many software approaches suffer large performance degradation, and hardware approaches have high logic and storage overhead. In this paper, we propose a flexible and light-weight hardware/software co-design approach to perform DIFT based on secure page allocation. Instead of associating every data with a taint tag, we aggregate data according to their taints, i.e., putting data with different attributes in separate memory pages. Our approach is a compiler-aided process with architecture support. The implementation and analysis show that the memory overhead is little, and our approach can protect critical information, including return address, indirect jump address, and system call IDs, from being overwritten by malicious users.<br /> <br /> <br /> == The General Idea ==<br /> <br /> == The Architectural Design ==<br /> <br /> == People ==<br /> <br /> * [[ Juan Carlos Martinez Santos]]<br /> <br /> == Publications ==</div>

Jcmartinez http://nueess.coe.neu.edu/nueess/index.php/Hardware-assisted_Security 2012-03-28T18:42:15Z

<p>Jcmartinez:&#32;</p> <hr /> <div>='''Description'''=<br /> <br /> As networking connections become pervasive for computer systems and embedded software contents increase dramatically, it becomes more convenient for hostile parties to utilize software vulnerability to attack embedded systems, such as personal digital assistants (PDAs), cell phones, networked sensors, and automotive electronics. <br /> <br /> The vulnerability of embedded systems carrying sensitive information to security attacks, ranging from common cybercrimes to terrorism, has become a very critical problem with far-reaching financial and social implications. For example, security is still the largest concern that prevents the adoption of mobile commence and secure messaging. In addition to the traditional metrics of performance, area, and power consumption, security has been regarded as one of the most important design goals for networked embedded systems. <br /> <br /> Compared to the general purpose and commodity desktop system, an embedded system presents advantages in allowing deployment of meaningful countermeasures across system architecture design. Building a secure embedded system, however, is a complex task that requires multidisciplinary research across different system layers and spanning various design stages, including circuits, processors, Operating System (OS), compiler, system platform, etc. It is especially challenging to find efficient solutions granting system immunity to a broad range of evolving attacks, considering the stringent constraints of embedded systems on computing capability, memory, and battery power and the tamper-prone insecure environment.<br /> <br /> ='''Projects'''=<br /> *[[Multi-thread isolation]]<br /> *[[DIFT for multi-thread applications on multi-core architectures]]<br /> *[[Dynamic Information Flow Tracking]]<br /> *[[Anomalous Path Detection]]<br /> <br /> ='''People'''=<br /> <br /> * [[Juan Carlos Martinez Santos]]<br /> <br /> ='''Publications'''=<br /> '' Conference Papers ''<br /> *J. C. Martinez Santos, Y. Fei, and Z. J. Shi, “PIFT: Efficient dynamic information flow tracking using secure page allocation,” in WkShp on Embedded System Security (WESS) (held in conjunction with Embedded Systems Week), Oct. 2009.<br /> *J. C. Martinez Santos and Y. Fei, “Leveraging speculative architectures for run-time program validation,” in Proc. IEEE Int. Conf. Computer Design, Oct. 2008.</div>

Jcmartinez http://nueess.coe.neu.edu/nueess/index.php/Hardware-assisted_Security 2012-03-28T18:39:29Z

<p>Jcmartinez:&#32;</p> <hr /> <div>='''Description'''=<br /> <br /> As networking connections become pervasive for computer systems and embedded software contents increase dramatically, it becomes more convenient for hostile parties to utilize software vulnerability to attack embedded systems, such as personal digital assistants (PDAs), cell phones, networked sensors, and automotive electronics. <br /> <br /> The vulnerability of embedded systems carrying sensitive information to security attacks, ranging from common cybercrimes to terrorism, has become a very critical problem with far-reaching financial and social implications. For example, security is still the largest concern that prevents the adoption of mobile commence and secure messaging. In addition to the traditional metrics of performance, area, and power consumption, security has been regarded as one of the most important design goals for networked embedded systems. <br /> <br /> Compared to the general purpose and commodity desktop system, an embedded system presents advantages in allowing deployment of meaningful countermeasures across system architecture design. Building a secure embedded system, however, is a complex task that requires multidisciplinary research across different system layers and spanning various design stages, including circuits, processors, Operating System (OS), compiler, system platform, etc. It is especially challenging to find efficient solutions granting system immunity to a broad range of evolving attacks, considering the stringent constraints of embedded systems on computing capability, memory, and battery power and the tamper-prone insecure environment.<br /> <br /> ='''Projects'''=<br /> *[[Multi-thread isolation]]<br /> *[[DIFT for multi-thread applications on multi-core architectures]]<br /> *[[Secure Page Allocation for Efficient Dynamic Information Flow Tracking]]<br /> *[[Anomalous Path Detection]]<br /> <br /> ='''People'''=<br /> <br /> * [[Juan Carlos Martinez Santos]]<br /> <br /> ='''Publications'''=<br /> '' Conference Papers ''<br /> *J. C. Martinez Santos, Y. Fei, and Z. J. Shi, “PIFT: Efficient dynamic information flow tracking using secure page allocation,” in WkShp on Embedded System Security (WESS) (held in conjunction with Embedded Systems Week), Oct. 2009.<br /> *J. C. Martinez Santos and Y. Fei, “Leveraging speculative architectures for run-time program validation,” in Proc. IEEE Int. Conf. Computer Design, Oct. 2008.</div>

Jcmartinez http://nueess.coe.neu.edu/nueess/index.php/Dynamic_Information_Flow_Tracking 2012-03-28T18:38:09Z

<p>Jcmartinez:&#32;/* Abstract */</p> <hr /> <div>== Abstract ==<br /> <br /> Dynamic information flow tracking (DIFT) is an effective security countermeasure for both low-level memory corruptions and high-level semantic attacks. However, many software approaches suffer large performance degradation, and hardware approaches have high logic and storage overhead. In this paper, we propose a flexible and light-weight hardware/software co-design approach to perform DIFT based on secure page allocation. Instead of associating every data with a taint tag, we aggregate data according to their taints, i.e., putting data with different attributes in separate memory pages. Our approach is a compiler-aided process with architecture support. The implementation and analysis show that the memory overhead is little, and our approach can protect critical information, including return address, indirect jump address, and system call IDs, from being overwritten by malicious users.</div>

Jcmartinez http://nueess.coe.neu.edu/nueess/index.php/Anomalous_Path_Detection 2012-03-28T18:35:12Z

<p>Jcmartinez:&#32;/* Motivation */</p> <hr /> <div>== Overview ==<br /> <br /> Program execution can be tampered by malicious attackers through exploiting software vulnerabilities. Changing the program behavior by compromising control data and decision data has become the most serious threat in computer system security. Although several hardware approaches have been presented to validate program execution, they either incur great hardware overhead or introduce false alarms. <br /> <br /> We propose a new hardware-based approach by leveraging the existing speculative architectures for run-time program validation. The on-chip branch target buffer (BTB) is utilized as a cache of the legitimate control flow transfers stored in a secure memory region. In addition, the BTB is extended to store the correct program path information. At each indirect branch site, the BTB is used to validate the decision history of previous conditional branches and monitor the following execution path at run-time. <br /> <br /> Implementation of this approach is transparent to the upper operating system and programs. Thus, it is applicable to legacy code. Because of good code locality of the executable programs and effectiveness of branch prediction, the frequency of control-flow validations against the secure off-chip memory is low. Our experimental results show a negligible performance penalty and small storage overhead.<br /> <br /> <br /> == Motivation ==<br /> <br /> When control flow attacks are inflicted on a system, the program execution can be directed to either malicious code injected by the attacker or some existing code that would not otherwise execute at that moment. It is the execution of the compromised control instructions that deviate from its expected behavior. <br /> <br /> To prevent control flow attacks, our micro-architecture level mechanism validates both control flow transfers and execution paths. The program execution monitoring is sampled at run-time at the sites of indirect branches, instead of every conditional branch or jump. Thus, the performance and storage overhead incurred by the monitoring is reduced greatly. However, since the checking is carried out less frequently, the coverage of each checking process has to be adequate for the program to reduce the false negative rate of validation.<br /> <br /> <br /> == Our approach ==<br /> <br /> we introduce a novel approach of protecting program execution at the micro-architectural level. We propose to monitor control-flow transfers and execution paths at the super block granularity. At each checking point (indirect branch site), dynamic program execution information is compared against a full record set (FRS) stored in a secure memory region, including legitimate target addresses, execution paths, and size of the super block. In addition, behavior reference for future program execution is also prefetched for later monitoring. To enable fast validation, we consider introducing a cache architecture for the FRS in the memory. As branch prediction schemes have been widely adopted in embedded processors, the on-chip branch target buffer (BTB) can be used as a perfect cache for the FRS. <br /> <br /> We propose a mechanism to ensure security for the BTB, i.e., avoiding any possible pollution from the tampered memory. We find that the validation mechanism only needs to be activated for those indirect branches that are mis-predicted by the BTB, in terms of direction, address, or execution history. The rare access of the external FRS results in much less performance degradation than other hardware schemes. The modification to the processor architecture is minor on top of the branch prediction structure and is transparent to the upper operating system and programs. Thus, legacy code can run on the secure processor without recompilations.<br /> <br /> == Extending the BTB ==<br /> [[File:preditor.png |thumb|right|350px|Regular branch prediction flow enhanced with security features]]<br /> In execution stage, the system has to compare the dynamic BHSR, PBPC, and size against the ICS in the BTB entry. If the history matches as well, it is a history hit, and the program execution will continue as normal. Otherwise, it is a history mis-prediction: the history paths associated with the TPC in the BTB do not include the history just seen. The tuple of {BPC, computed NPC, BHSR, PBPC, SIZE} has to be sent to the external memory (FRS) for further validation. This is labeled 3. Only when it misses again, a security alarm will be raised.<br /> <br /> In traditional architecture, on an address mis-prediction site, the BTB entry is just updated when the next PC is resolved from the instruction. However, since an indirect target address mis-prediction may also be caused by security attacks, in our enhanced architecture, the external memory has to be checked before the corresponding entry in the BTB is updated with the matched ICS. This site is labeled 2. At a direction mis-prediction site where there is a BTB entry for the instruction but the instruction is actually not taken, the entry is deleted and the fetched TPC is squashed. There is normally a mis-prediction penalty for these remedy actions.<br /> <br /> On the leftmost side of the flow diagram, if no entry is found in the BTB for the current PC, the instruction may be a regular data path instruction or a control instruction falling through. In the subsequent ID stage, if the instruction is found to be a taken control instruction, it is a direction mis-prediction, and the address is not cached in the BTB. Before a new entry is inserted to the BTB, the tuple of {BPC, computed NPC, BHSR, PBPC, SIZE} has to be validated against the record in memory. This site is labeled 1. Since the BTB has limited capacity, a replacement policy, e.g., least recently used (LRU), may be employed to find a victim to evict for multi-associativity BTB.<br /> <br /> == Architectural Support ==<br /> [[File:architecture.png |thumb|right|350px|The architecture support in processor pipeline for control flow validation]]<br /> For every indirect branch instruction, the BPC is sent to the BTB during the fetch stage. After the execution stage, the dynamic information extracted, including next target PC (NTPC), BHSR, PBPC, and SIZE is also sent to the BTB for validation. On any mis-prediction, the full record set (FRS) in the secure memory is accessed, and the corresponding indirect control signature (ICS) is brought into the processor. With the expected path vector fetched into the processor pipeline, the program execution is monitored at run-time on a basic block basis.<br /> <br /> == People ==<br /> <br /> * [[Juan Carlos Martinez Santos]]<br /> <br /> == Publications ==<br /> <br /> *J. C. Martinez Santos and Y. Fei, “Leveraging speculative architectures for run-time program validation,” in Proc. IEEE Int. Conf. Computer Design, Oct. 2008.</div>

Jcmartinez http://nueess.coe.neu.edu/nueess/index.php/File:Architecture.png 2012-03-28T18:31:29Z

<p>Jcmartinez:&#32;</p> <hr /> <div></div>

Jcmartinez http://nueess.coe.neu.edu/nueess/index.php/Anomalous_Path_Detection 2012-03-28T18:31:07Z

<p>Jcmartinez:&#32;/* Architectural Support */</p> <hr /> <div>== Overview ==<br /> <br /> Program execution can be tampered by malicious attackers through exploiting software vulnerabilities. Changing the program behavior by compromising control data and decision data has become the most serious threat in computer system security. Although several hardware approaches have been presented to validate program execution, they either incur great hardware overhead or introduce false alarms. <br /> <br /> We propose a new hardware-based approach by leveraging the existing speculative architectures for run-time program validation. The on-chip branch target buffer (BTB) is utilized as a cache of the legitimate control flow transfers stored in a secure memory region. In addition, the BTB is extended to store the correct program path information. At each indirect branch site, the BTB is used to validate the decision history of previous conditional branches and monitor the following execution path at run-time. <br /> <br /> Implementation of this approach is transparent to the upper operating system and programs. Thus, it is applicable to legacy code. Because of good code locality of the executable programs and effectiveness of branch prediction, the frequency of control-flow validations against the secure off-chip memory is low. Our experimental results show a negligible performance penalty and small storage overhead.<br /> <br /> <br /> == Motivation ==<br /> <br /> When control flow attacks are inflicted on a system, the program execution can be directed to either malicious code injected by the attacker or some existing code that would not otherwise execute at that moment. It is the execution of the compromised control instructions that deviate from its expected behavior. <br /> <br /> To prevent control flow attacks, our micro-architecture level mechanism validates both control flow transfers and execution paths. The program execution monitoring is sampled at run-time at the sites of indirect branches, instead of every conditional branch or jump. Thus, the performance and storage overhead incurred by the monitoring is reduced greatly. However, since the checking is carried out less frequently, the coverage of each checking process has to be adequate for the program to reduce the false negative rate of validation.<br /> <br /> <br /> == Extending the BTB ==<br /> [[File:preditor.png |thumb|right|350px|Regular branch prediction flow enhanced with security features]]<br /> In execution stage, the system has to compare the dynamic BHSR, PBPC, and size against the ICS in the BTB entry. If the history matches as well, it is a history hit, and the program execution will continue as normal. Otherwise, it is a history mis-prediction: the history paths associated with the TPC in the BTB do not include the history just seen. The tuple of {BPC, computed NPC, BHSR, PBPC, SIZE} has to be sent to the external memory (FRS) for further validation. This is labeled 3. Only when it misses again, a security alarm will be raised.<br /> <br /> In traditional architecture, on an address mis-prediction site, the BTB entry is just updated when the next PC is resolved from the instruction. However, since an indirect target address mis-prediction may also be caused by security attacks, in our enhanced architecture, the external memory has to be checked before the corresponding entry in the BTB is updated with the matched ICS. This site is labeled 2. At a direction mis-prediction site where there is a BTB entry for the instruction but the instruction is actually not taken, the entry is deleted and the fetched TPC is squashed. There is normally a mis-prediction penalty for these remedy actions.<br /> <br /> On the leftmost side of the flow diagram, if no entry is found in the BTB for the current PC, the instruction may be a regular data path instruction or a control instruction falling through. In the subsequent ID stage, if the instruction is found to be a taken control instruction, it is a direction mis-prediction, and the address is not cached in the BTB. Before a new entry is inserted to the BTB, the tuple of {BPC, computed NPC, BHSR, PBPC, SIZE} has to be validated against the record in memory. This site is labeled 1. Since the BTB has limited capacity, a replacement policy, e.g., least recently used (LRU), may be employed to find a victim to evict for multi-associativity BTB.<br /> <br /> == Architectural Support ==<br /> [[File:architecture.png |thumb|right|350px|The architecture support in processor pipeline for control flow validation]]<br /> For every indirect branch instruction, the BPC is sent to the BTB during the fetch stage. After the execution stage, the dynamic information extracted, including next target PC (NTPC), BHSR, PBPC, and SIZE is also sent to the BTB for validation. On any mis-prediction, the full record set (FRS) in the secure memory is accessed, and the corresponding indirect control signature (ICS) is brought into the processor. With the expected path vector fetched into the processor pipeline, the program execution is monitored at run-time on a basic block basis.<br /> <br /> == People ==<br /> <br /> * [[Juan Carlos Martinez Santos]]<br /> <br /> == Publications ==<br /> <br /> *J. C. Martinez Santos and Y. Fei, “Leveraging speculative architectures for run-time program validation,” in Proc. IEEE Int. Conf. Computer Design, Oct. 2008.</div>

Jcmartinez http://nueess.coe.neu.edu/nueess/index.php/Anomalous_Path_Detection 2012-03-28T18:25:12Z

<p>Jcmartinez:&#32;/* People */</p> <hr /> <div>== Overview ==<br /> <br /> Program execution can be tampered by malicious attackers through exploiting software vulnerabilities. Changing the program behavior by compromising control data and decision data has become the most serious threat in computer system security. Although several hardware approaches have been presented to validate program execution, they either incur great hardware overhead or introduce false alarms. <br /> <br /> We propose a new hardware-based approach by leveraging the existing speculative architectures for run-time program validation. The on-chip branch target buffer (BTB) is utilized as a cache of the legitimate control flow transfers stored in a secure memory region. In addition, the BTB is extended to store the correct program path information. At each indirect branch site, the BTB is used to validate the decision history of previous conditional branches and monitor the following execution path at run-time. <br /> <br /> Implementation of this approach is transparent to the upper operating system and programs. Thus, it is applicable to legacy code. Because of good code locality of the executable programs and effectiveness of branch prediction, the frequency of control-flow validations against the secure off-chip memory is low. Our experimental results show a negligible performance penalty and small storage overhead.<br /> <br /> <br /> == Motivation ==<br /> <br /> When control flow attacks are inflicted on a system, the program execution can be directed to either malicious code injected by the attacker or some existing code that would not otherwise execute at that moment. It is the execution of the compromised control instructions that deviate from its expected behavior. <br /> <br /> To prevent control flow attacks, our micro-architecture level mechanism validates both control flow transfers and execution paths. The program execution monitoring is sampled at run-time at the sites of indirect branches, instead of every conditional branch or jump. Thus, the performance and storage overhead incurred by the monitoring is reduced greatly. However, since the checking is carried out less frequently, the coverage of each checking process has to be adequate for the program to reduce the false negative rate of validation.<br /> <br /> <br /> == Extending the BTB ==<br /> [[File:preditor.png |thumb|right|350px|Regular branch prediction flow enhanced with security features]]<br /> In execution stage, the system has to compare the dynamic BHSR, PBPC, and size against the ICS in the BTB entry. If the history matches as well, it is a history hit, and the program execution will continue as normal. Otherwise, it is a history mis-prediction: the history paths associated with the TPC in the BTB do not include the history just seen. The tuple of {BPC, computed NPC, BHSR, PBPC, SIZE} has to be sent to the external memory (FRS) for further validation. This is labeled 3. Only when it misses again, a security alarm will be raised.<br /> <br /> In traditional architecture, on an address mis-prediction site, the BTB entry is just updated when the next PC is resolved from the instruction. However, since an indirect target address mis-prediction may also be caused by security attacks, in our enhanced architecture, the external memory has to be checked before the corresponding entry in the BTB is updated with the matched ICS. This site is labeled 2. At a direction mis-prediction site where there is a BTB entry for the instruction but the instruction is actually not taken, the entry is deleted and the fetched TPC is squashed. There is normally a mis-prediction penalty for these remedy actions.<br /> <br /> On the leftmost side of the flow diagram, if no entry is found in the BTB for the current PC, the instruction may be a regular data path instruction or a control instruction falling through. In the subsequent ID stage, if the instruction is found to be a taken control instruction, it is a direction mis-prediction, and the address is not cached in the BTB. Before a new entry is inserted to the BTB, the tuple of {BPC, computed NPC, BHSR, PBPC, SIZE} has to be validated against the record in memory. This site is labeled 1. Since the BTB has limited capacity, a replacement policy, e.g., least recently used (LRU), may be employed to find a victim to evict for multi-associativity BTB.<br /> <br /> == Architectural Support ==<br /> <br /> == People ==<br /> <br /> * [[Juan Carlos Martinez Santos]]<br /> <br /> == Publications ==<br /> <br /> *J. C. Martinez Santos and Y. Fei, “Leveraging speculative architectures for run-time program validation,” in Proc. IEEE Int. Conf. Computer Design, Oct. 2008.</div>

Jcmartinez http://nueess.coe.neu.edu/nueess/index.php/Anomalous_Path_Detection 2012-03-28T18:24:36Z

<p>Jcmartinez:&#32;/* Extending the BTB */</p> <hr /> <div>== Overview ==<br /> <br /> Program execution can be tampered by malicious attackers through exploiting software vulnerabilities. Changing the program behavior by compromising control data and decision data has become the most serious threat in computer system security. Although several hardware approaches have been presented to validate program execution, they either incur great hardware overhead or introduce false alarms. <br /> <br /> We propose a new hardware-based approach by leveraging the existing speculative architectures for run-time program validation. The on-chip branch target buffer (BTB) is utilized as a cache of the legitimate control flow transfers stored in a secure memory region. In addition, the BTB is extended to store the correct program path information. At each indirect branch site, the BTB is used to validate the decision history of previous conditional branches and monitor the following execution path at run-time. <br /> <br /> Implementation of this approach is transparent to the upper operating system and programs. Thus, it is applicable to legacy code. Because of good code locality of the executable programs and effectiveness of branch prediction, the frequency of control-flow validations against the secure off-chip memory is low. Our experimental results show a negligible performance penalty and small storage overhead.<br /> <br /> <br /> == Motivation ==<br /> <br /> When control flow attacks are inflicted on a system, the program execution can be directed to either malicious code injected by the attacker or some existing code that would not otherwise execute at that moment. It is the execution of the compromised control instructions that deviate from its expected behavior. <br /> <br /> To prevent control flow attacks, our micro-architecture level mechanism validates both control flow transfers and execution paths. The program execution monitoring is sampled at run-time at the sites of indirect branches, instead of every conditional branch or jump. Thus, the performance and storage overhead incurred by the monitoring is reduced greatly. However, since the checking is carried out less frequently, the coverage of each checking process has to be adequate for the program to reduce the false negative rate of validation.<br /> <br /> <br /> == Extending the BTB ==<br /> [[File:preditor.png |thumb|right|350px|Regular branch prediction flow enhanced with security features]]<br /> In execution stage, the system has to compare the dynamic BHSR, PBPC, and size against the ICS in the BTB entry. If the history matches as well, it is a history hit, and the program execution will continue as normal. Otherwise, it is a history mis-prediction: the history paths associated with the TPC in the BTB do not include the history just seen. The tuple of {BPC, computed NPC, BHSR, PBPC, SIZE} has to be sent to the external memory (FRS) for further validation. This is labeled 3. Only when it misses again, a security alarm will be raised.<br /> <br /> In traditional architecture, on an address mis-prediction site, the BTB entry is just updated when the next PC is resolved from the instruction. However, since an indirect target address mis-prediction may also be caused by security attacks, in our enhanced architecture, the external memory has to be checked before the corresponding entry in the BTB is updated with the matched ICS. This site is labeled 2. At a direction mis-prediction site where there is a BTB entry for the instruction but the instruction is actually not taken, the entry is deleted and the fetched TPC is squashed. There is normally a mis-prediction penalty for these remedy actions.<br /> <br /> On the leftmost side of the flow diagram, if no entry is found in the BTB for the current PC, the instruction may be a regular data path instruction or a control instruction falling through. In the subsequent ID stage, if the instruction is found to be a taken control instruction, it is a direction mis-prediction, and the address is not cached in the BTB. Before a new entry is inserted to the BTB, the tuple of {BPC, computed NPC, BHSR, PBPC, SIZE} has to be validated against the record in memory. This site is labeled 1. Since the BTB has limited capacity, a replacement policy, e.g., least recently used (LRU), may be employed to find a victim to evict for multi-associativity BTB.<br /> <br /> == People ==<br /> <br /> * [[Juan Carlos Martinez Santos]]<br /> <br /> == Publications ==<br /> <br /> *J. C. Martinez Santos and Y. Fei, “Leveraging speculative architectures for run-time program validation,” in Proc. IEEE Int. Conf. Computer Design, Oct. 2008.</div>

Jcmartinez http://nueess.coe.neu.edu/nueess/index.php/Anomalous_Path_Detection 2012-03-28T18:22:39Z

<p>Jcmartinez:&#32;/* Extending the BTB */</p> <hr /> <div>== Overview ==<br /> <br /> Program execution can be tampered by malicious attackers through exploiting software vulnerabilities. Changing the program behavior by compromising control data and decision data has become the most serious threat in computer system security. Although several hardware approaches have been presented to validate program execution, they either incur great hardware overhead or introduce false alarms. <br /> <br /> We propose a new hardware-based approach by leveraging the existing speculative architectures for run-time program validation. The on-chip branch target buffer (BTB) is utilized as a cache of the legitimate control flow transfers stored in a secure memory region. In addition, the BTB is extended to store the correct program path information. At each indirect branch site, the BTB is used to validate the decision history of previous conditional branches and monitor the following execution path at run-time. <br /> <br /> Implementation of this approach is transparent to the upper operating system and programs. Thus, it is applicable to legacy code. Because of good code locality of the executable programs and effectiveness of branch prediction, the frequency of control-flow validations against the secure off-chip memory is low. Our experimental results show a negligible performance penalty and small storage overhead.<br /> <br /> <br /> == Motivation ==<br /> <br /> When control flow attacks are inflicted on a system, the program execution can be directed to either malicious code injected by the attacker or some existing code that would not otherwise execute at that moment. It is the execution of the compromised control instructions that deviate from its expected behavior. <br /> <br /> To prevent control flow attacks, our micro-architecture level mechanism validates both control flow transfers and execution paths. The program execution monitoring is sampled at run-time at the sites of indirect branches, instead of every conditional branch or jump. Thus, the performance and storage overhead incurred by the monitoring is reduced greatly. However, since the checking is carried out less frequently, the coverage of each checking process has to be adequate for the program to reduce the false negative rate of validation.<br /> <br /> <br /> == Extending the BTB ==<br /> [[File:preditor.png |thumb|right|350px|Regular branch prediction flow enhanced with security features]]<br /> When an instruction is fetched from the instruction memory (in IF stage), the same PC address is used to access the BTB. A hit at this point indicates that the instruction to be executed is a control instruction. The predicted target PC (TPC) in BTB is then used as the next PC (NPC) to fetch a new instruction in the next pipeline stage (ID), rather than waiting until the later stage to use the NPC computed in EX stage for fetching instruction, avoiding branch stalls. Meanwhile, according to the instruction type, a direction prediction or computation is performed. If the branch is computed to be taken (direction hit), the TPC from the BTB will be compared with the computed NPC in the EX stage. If these two values match (address hit), both the branch direction and the target prediction are correct. However, one more validation has to be done for indirect control instructions in our approach.<br /> <br /> In execution stage, the system has to compare the dynamic BHSR, PBPC, and size against the ICS in the BTB entry. If the history matches as well, it is a history hit, and the program execution will continue as normal. Otherwise, it is a history mis-prediction: the history paths associated with the TPC in the BTB do not include the history just seen. The tuple of {BPC, computed NPC, BHSR, PBPC, SIZE} has to be sent to the external memory (FRS) for further validation. This is labeled 3. Only when it misses again, a security alarm will be raised.<br /> In traditional architecture, on an address mis-prediction site, the BTB entry is just updated<br /> when the next PC is resolved from the instruction. However, since an indirect target<br /> address mis-prediction may also be caused by security attacks, in our enhanced architecture,<br /> the external memory has to be checked before the corresponding entry in the BTB is<br /> updated with the matched ICS. This site is labeled 2. At a direction mis-prediction<br /> site where there is a BTB entry for the instruction but the instruction is actually not taken,<br /> the entry is deleted and the fetched TPC is squashed. There is normally a mis-prediction<br /> penalty for these remedy actions.<br /> <br /> == People ==<br /> <br /> * [[Juan Carlos Martinez Santos]]<br /> <br /> == Publications ==<br /> <br /> *J. C. Martinez Santos and Y. Fei, “Leveraging speculative architectures for run-time program validation,” in Proc. IEEE Int. Conf. Computer Design, Oct. 2008.</div>

Jcmartinez http://nueess.coe.neu.edu/nueess/index.php/File:Preditor.png 2012-03-28T18:20:10Z

<p>Jcmartinez:&#32;</p> <hr /> <div></div>

Jcmartinez http://nueess.coe.neu.edu/nueess/index.php/Anomalous_Path_Detection 2012-03-28T18:19:46Z

<p>Jcmartinez:&#32;/* Extending the BTB */</p> <hr /> <div>== Overview ==<br /> <br /> Program execution can be tampered by malicious attackers through exploiting software vulnerabilities. Changing the program behavior by compromising control data and decision data has become the most serious threat in computer system security. Although several hardware approaches have been presented to validate program execution, they either incur great hardware overhead or introduce false alarms. <br /> <br /> We propose a new hardware-based approach by leveraging the existing speculative architectures for run-time program validation. The on-chip branch target buffer (BTB) is utilized as a cache of the legitimate control flow transfers stored in a secure memory region. In addition, the BTB is extended to store the correct program path information. At each indirect branch site, the BTB is used to validate the decision history of previous conditional branches and monitor the following execution path at run-time. <br /> <br /> Implementation of this approach is transparent to the upper operating system and programs. Thus, it is applicable to legacy code. Because of good code locality of the executable programs and effectiveness of branch prediction, the frequency of control-flow validations against the secure off-chip memory is low. Our experimental results show a negligible performance penalty and small storage overhead.<br /> <br /> <br /> == Motivation ==<br /> <br /> When control flow attacks are inflicted on a system, the program execution can be directed to either malicious code injected by the attacker or some existing code that would not otherwise execute at that moment. It is the execution of the compromised control instructions that deviate from its expected behavior. <br /> <br /> To prevent control flow attacks, our micro-architecture level mechanism validates both control flow transfers and execution paths. The program execution monitoring is sampled at run-time at the sites of indirect branches, instead of every conditional branch or jump. Thus, the performance and storage overhead incurred by the monitoring is reduced greatly. However, since the checking is carried out less frequently, the coverage of each checking process has to be adequate for the program to reduce the false negative rate of validation.<br /> <br /> <br /> == Extending the BTB ==<br /> [[File:preditor.png |thumb|right|350px|Regular branch prediction flow enhanced with security features]]<br /> Fig. 4 illustrates the branch prediction flow using a BTB in a simple five-stage pipeline<br /> architecture. The solid objects and lines are for the regular branch prediction scheme. The<br /> flow is also extended with some enhancements for control flow transfer and execution path<br /> validation, as shown in dashed lines and objects, which will replace the original operations.<br /> <br /> == People ==<br /> <br /> * [[Juan Carlos Martinez Santos]]<br /> <br /> == Publications ==<br /> <br /> *J. C. Martinez Santos and Y. Fei, “Leveraging speculative architectures for run-time program validation,” in Proc. IEEE Int. Conf. Computer Design, Oct. 2008.</div>

Jcmartinez http://nueess.coe.neu.edu/nueess/index.php/Anomalous_Path_Detection 2012-03-28T18:19:04Z

<p>Jcmartinez:&#32;/* Extending the BTB */</p> <hr /> <div>== Overview ==<br /> <br /> Program execution can be tampered by malicious attackers through exploiting software vulnerabilities. Changing the program behavior by compromising control data and decision data has become the most serious threat in computer system security. Although several hardware approaches have been presented to validate program execution, they either incur great hardware overhead or introduce false alarms. <br /> <br /> We propose a new hardware-based approach by leveraging the existing speculative architectures for run-time program validation. The on-chip branch target buffer (BTB) is utilized as a cache of the legitimate control flow transfers stored in a secure memory region. In addition, the BTB is extended to store the correct program path information. At each indirect branch site, the BTB is used to validate the decision history of previous conditional branches and monitor the following execution path at run-time. <br /> <br /> Implementation of this approach is transparent to the upper operating system and programs. Thus, it is applicable to legacy code. Because of good code locality of the executable programs and effectiveness of branch prediction, the frequency of control-flow validations against the secure off-chip memory is low. Our experimental results show a negligible performance penalty and small storage overhead.<br /> <br /> <br /> == Motivation ==<br /> <br /> When control flow attacks are inflicted on a system, the program execution can be directed to either malicious code injected by the attacker or some existing code that would not otherwise execute at that moment. It is the execution of the compromised control instructions that deviate from its expected behavior. <br /> <br /> To prevent control flow attacks, our micro-architecture level mechanism validates both control flow transfers and execution paths. The program execution monitoring is sampled at run-time at the sites of indirect branches, instead of every conditional branch or jump. Thus, the performance and storage overhead incurred by the monitoring is reduced greatly. However, since the checking is carried out less frequently, the coverage of each checking process has to be adequate for the program to reduce the false negative rate of validation.<br /> <br /> <br /> == Extending the BTB ==<br /> [[File:preditor.png |thumb|right|350px|Microgrid for a community]]<br /> Fig. 4 illustrates the branch prediction flow using a BTB in a simple five-stage pipeline<br /> architecture. The solid objects and lines are for the regular branch prediction scheme. The<br /> flow is also extended with some enhancements for control flow transfer and execution path<br /> validation, as shown in dashed lines and objects, which will replace the original operations.<br /> <br /> == People ==<br /> <br /> * [[Juan Carlos Martinez Santos]]<br /> <br /> == Publications ==<br /> <br /> *J. C. Martinez Santos and Y. Fei, “Leveraging speculative architectures for run-time program validation,” in Proc. IEEE Int. Conf. Computer Design, Oct. 2008.</div>

Jcmartinez http://nueess.coe.neu.edu/nueess/index.php/Anomalous_Path_Detection 2012-03-28T18:18:18Z

<p>Jcmartinez:&#32;/* Extending the BTB */</p> <hr /> <div>== Overview ==<br /> <br /> Program execution can be tampered by malicious attackers through exploiting software vulnerabilities. Changing the program behavior by compromising control data and decision data has become the most serious threat in computer system security. Although several hardware approaches have been presented to validate program execution, they either incur great hardware overhead or introduce false alarms. <br /> <br /> We propose a new hardware-based approach by leveraging the existing speculative architectures for run-time program validation. The on-chip branch target buffer (BTB) is utilized as a cache of the legitimate control flow transfers stored in a secure memory region. In addition, the BTB is extended to store the correct program path information. At each indirect branch site, the BTB is used to validate the decision history of previous conditional branches and monitor the following execution path at run-time. <br /> <br /> Implementation of this approach is transparent to the upper operating system and programs. Thus, it is applicable to legacy code. Because of good code locality of the executable programs and effectiveness of branch prediction, the frequency of control-flow validations against the secure off-chip memory is low. Our experimental results show a negligible performance penalty and small storage overhead.<br /> <br /> <br /> == Motivation ==<br /> <br /> When control flow attacks are inflicted on a system, the program execution can be directed to either malicious code injected by the attacker or some existing code that would not otherwise execute at that moment. It is the execution of the compromised control instructions that deviate from its expected behavior. <br /> <br /> To prevent control flow attacks, our micro-architecture level mechanism validates both control flow transfers and execution paths. The program execution monitoring is sampled at run-time at the sites of indirect branches, instead of every conditional branch or jump. Thus, the performance and storage overhead incurred by the monitoring is reduced greatly. However, since the checking is carried out less frequently, the coverage of each checking process has to be adequate for the program to reduce the false negative rate of validation.<br /> <br /> <br /> == Extending the BTB ==<br /> [[File:Preditor.png |thumb|right|350px|Microgrid for a community]]<br /> Fig. 4 illustrates the branch prediction flow using a BTB in a simple five-stage pipeline<br /> architecture. The solid objects and lines are for the regular branch prediction scheme. The<br /> flow is also extended with some enhancements for control flow transfer and execution path<br /> validation, as shown in dashed lines and objects, which will replace the original operations.<br /> <br /> == People ==<br /> <br /> * [[Juan Carlos Martinez Santos]]<br /> <br /> == Publications ==<br /> <br /> *J. C. Martinez Santos and Y. Fei, “Leveraging speculative architectures for run-time program validation,” in Proc. IEEE Int. Conf. Computer Design, Oct. 2008.</div>

Jcmartinez http://nueess.coe.neu.edu/nueess/index.php/File:Predictor.png 2012-03-28T18:17:51Z

<p>Jcmartinez:&#32;</p> <hr /> <div></div>

Jcmartinez http://nueess.coe.neu.edu/nueess/index.php/Anomalous_Path_Detection 2012-03-28T18:12:57Z

<p>Jcmartinez:&#32;/* Extending the BTB */</p> <hr /> <div>== Overview ==<br /> <br /> Program execution can be tampered by malicious attackers through exploiting software vulnerabilities. Changing the program behavior by compromising control data and decision data has become the most serious threat in computer system security. Although several hardware approaches have been presented to validate program execution, they either incur great hardware overhead or introduce false alarms. <br /> <br /> We propose a new hardware-based approach by leveraging the existing speculative architectures for run-time program validation. The on-chip branch target buffer (BTB) is utilized as a cache of the legitimate control flow transfers stored in a secure memory region. In addition, the BTB is extended to store the correct program path information. At each indirect branch site, the BTB is used to validate the decision history of previous conditional branches and monitor the following execution path at run-time. <br /> <br /> Implementation of this approach is transparent to the upper operating system and programs. Thus, it is applicable to legacy code. Because of good code locality of the executable programs and effectiveness of branch prediction, the frequency of control-flow validations against the secure off-chip memory is low. Our experimental results show a negligible performance penalty and small storage overhead.<br /> <br /> <br /> == Motivation ==<br /> <br /> When control flow attacks are inflicted on a system, the program execution can be directed to either malicious code injected by the attacker or some existing code that would not otherwise execute at that moment. It is the execution of the compromised control instructions that deviate from its expected behavior. <br /> <br /> To prevent control flow attacks, our micro-architecture level mechanism validates both control flow transfers and execution paths. The program execution monitoring is sampled at run-time at the sites of indirect branches, instead of every conditional branch or jump. Thus, the performance and storage overhead incurred by the monitoring is reduced greatly. However, since the checking is carried out less frequently, the coverage of each checking process has to be adequate for the program to reduce the false negative rate of validation.<br /> <br /> <br /> == Extending the BTB ==<br /> [[File:MicrogridScheme.png |thumb|right|350px|Microgrid for a community]]<br /> Fig. 4 illustrates the branch prediction flow using a BTB in a simple five-stage pipeline<br /> architecture. The solid objects and lines are for the regular branch prediction scheme. The<br /> flow is also extended with some enhancements for control flow transfer and execution path<br /> validation, as shown in dashed lines and objects, which will replace the original operations.<br /> <br /> == People ==<br /> <br /> * [[Juan Carlos Martinez Santos]]<br /> <br /> == Publications ==<br /> <br /> *J. C. Martinez Santos and Y. Fei, “Leveraging speculative architectures for run-time program validation,” in Proc. IEEE Int. Conf. Computer Design, Oct. 2008.</div>

Jcmartinez http://nueess.coe.neu.edu/nueess/index.php/Anomalous_Path_Detection 2012-03-28T18:12:10Z

<p>Jcmartinez:&#32;/* Extending the BTB */</p> <hr /> <div>== Overview ==<br /> <br /> Program execution can be tampered by malicious attackers through exploiting software vulnerabilities. Changing the program behavior by compromising control data and decision data has become the most serious threat in computer system security. Although several hardware approaches have been presented to validate program execution, they either incur great hardware overhead or introduce false alarms. <br /> <br /> We propose a new hardware-based approach by leveraging the existing speculative architectures for run-time program validation. The on-chip branch target buffer (BTB) is utilized as a cache of the legitimate control flow transfers stored in a secure memory region. In addition, the BTB is extended to store the correct program path information. At each indirect branch site, the BTB is used to validate the decision history of previous conditional branches and monitor the following execution path at run-time. <br /> <br /> Implementation of this approach is transparent to the upper operating system and programs. Thus, it is applicable to legacy code. Because of good code locality of the executable programs and effectiveness of branch prediction, the frequency of control-flow validations against the secure off-chip memory is low. Our experimental results show a negligible performance penalty and small storage overhead.<br /> <br /> <br /> == Motivation ==<br /> <br /> When control flow attacks are inflicted on a system, the program execution can be directed to either malicious code injected by the attacker or some existing code that would not otherwise execute at that moment. It is the execution of the compromised control instructions that deviate from its expected behavior. <br /> <br /> To prevent control flow attacks, our micro-architecture level mechanism validates both control flow transfers and execution paths. The program execution monitoring is sampled at run-time at the sites of indirect branches, instead of every conditional branch or jump. Thus, the performance and storage overhead incurred by the monitoring is reduced greatly. However, since the checking is carried out less frequently, the coverage of each checking process has to be adequate for the program to reduce the false negative rate of validation.<br /> <br /> <br /> == Extending the BTB ==<br /> <br /> Fig. 4 illustrates the branch prediction flow using a BTB in a simple five-stage pipeline<br /> architecture. The solid objects and lines are for the regular branch prediction scheme. The<br /> flow is also extended with some enhancements for control flow transfer and execution path<br /> validation, as shown in dashed lines and objects, which will replace the original operations.<br /> <br /> == People ==<br /> <br /> * [[Juan Carlos Martinez Santos]]<br /> <br /> == Publications ==<br /> <br /> *J. C. Martinez Santos and Y. Fei, “Leveraging speculative architectures for run-time program validation,” in Proc. IEEE Int. Conf. Computer Design, Oct. 2008.</div>

Jcmartinez http://nueess.coe.neu.edu/nueess/index.php/Anomalous_Path_Detection 2012-03-28T18:10:18Z

<p>Jcmartinez:&#32;/* Motivation */</p> <hr /> <div>== Overview ==<br /> <br /> Program execution can be tampered by malicious attackers through exploiting software vulnerabilities. Changing the program behavior by compromising control data and decision data has become the most serious threat in computer system security. Although several hardware approaches have been presented to validate program execution, they either incur great hardware overhead or introduce false alarms. <br /> <br /> We propose a new hardware-based approach by leveraging the existing speculative architectures for run-time program validation. The on-chip branch target buffer (BTB) is utilized as a cache of the legitimate control flow transfers stored in a secure memory region. In addition, the BTB is extended to store the correct program path information. At each indirect branch site, the BTB is used to validate the decision history of previous conditional branches and monitor the following execution path at run-time. <br /> <br /> Implementation of this approach is transparent to the upper operating system and programs. Thus, it is applicable to legacy code. Because of good code locality of the executable programs and effectiveness of branch prediction, the frequency of control-flow validations against the secure off-chip memory is low. Our experimental results show a negligible performance penalty and small storage overhead.<br /> <br /> <br /> == Motivation ==<br /> <br /> When control flow attacks are inflicted on a system, the program execution can be directed to either malicious code injected by the attacker or some existing code that would not otherwise execute at that moment. It is the execution of the compromised control instructions that deviate from its expected behavior. <br /> <br /> To prevent control flow attacks, our micro-architecture level mechanism validates both control flow transfers and execution paths. The program execution monitoring is sampled at run-time at the sites of indirect branches, instead of every conditional branch or jump. Thus, the performance and storage overhead incurred by the monitoring is reduced greatly. However, since the checking is carried out less frequently, the coverage of each checking process has to be adequate for the program to reduce the false negative rate of validation.<br /> <br /> <br /> == Extending the BTB ==<br /> <br /> == People ==<br /> <br /> * [[Juan Carlos Martinez Santos]]<br /> <br /> == Publications ==<br /> <br /> *J. C. Martinez Santos and Y. Fei, “Leveraging speculative architectures for run-time program validation,” in Proc. IEEE Int. Conf. Computer Design, Oct. 2008.</div>

Jcmartinez http://nueess.coe.neu.edu/nueess/index.php/Anomalous_Path_Detection 2012-03-28T18:07:59Z

<p>Jcmartinez:&#32;/* Motivation */</p> <hr /> <div>== Overview ==<br /> <br /> Program execution can be tampered by malicious attackers through exploiting software vulnerabilities. Changing the program behavior by compromising control data and decision data has become the most serious threat in computer system security. Although several hardware approaches have been presented to validate program execution, they either incur great hardware overhead or introduce false alarms. <br /> <br /> We propose a new hardware-based approach by leveraging the existing speculative architectures for run-time program validation. The on-chip branch target buffer (BTB) is utilized as a cache of the legitimate control flow transfers stored in a secure memory region. In addition, the BTB is extended to store the correct program path information. At each indirect branch site, the BTB is used to validate the decision history of previous conditional branches and monitor the following execution path at run-time. <br /> <br /> Implementation of this approach is transparent to the upper operating system and programs. Thus, it is applicable to legacy code. Because of good code locality of the executable programs and effectiveness of branch prediction, the frequency of control-flow validations against the secure off-chip memory is low. Our experimental results show a negligible performance penalty and small storage overhead.<br /> <br /> <br /> == Motivation ==<br /> <br /> When control flow attacks are inflicted on a system, the program execution can be directed<br /> to either malicious code injected by the attacker or some existing code that would<br /> not otherwise execute at that moment. It is the execution of the compromised control instructions<br /> that deviate from its expected behavior. To prevent control flow attacks, our<br /> micro-architecture level mechanism validates both control flow transfers and execution<br /> paths. The program execution monitoring is sampled at run-time at the sites of indirect<br /> branches, instead of every conditional branch or jump [Zhang et al. 2005]. Thus, the performance<br /> and storage overhead incurred by the monitoring is reduced greatly. However,<br /> since the checking is carried out less frequently, the coverage of each checking process has<br /> to be adequate for the program to reduce the false negative rate of validation.<br /> <br /> == People ==<br /> <br /> * [[Juan Carlos Martinez Santos]]<br /> <br /> == Publications ==<br /> <br /> *J. C. Martinez Santos and Y. Fei, “Leveraging speculative architectures for run-time program validation,” in Proc. IEEE Int. Conf. Computer Design, Oct. 2008.</div>

Jcmartinez http://nueess.coe.neu.edu/nueess/index.php/Anomalous_Path_Detection 2012-03-28T18:07:37Z

<p>Jcmartinez:&#32;/* Overview */</p> <hr /> <div>== Overview ==<br /> <br /> Program execution can be tampered by malicious attackers through exploiting software vulnerabilities. Changing the program behavior by compromising control data and decision data has become the most serious threat in computer system security. Although several hardware approaches have been presented to validate program execution, they either incur great hardware overhead or introduce false alarms. <br /> <br /> We propose a new hardware-based approach by leveraging the existing speculative architectures for run-time program validation. The on-chip branch target buffer (BTB) is utilized as a cache of the legitimate control flow transfers stored in a secure memory region. In addition, the BTB is extended to store the correct program path information. At each indirect branch site, the BTB is used to validate the decision history of previous conditional branches and monitor the following execution path at run-time. <br /> <br /> Implementation of this approach is transparent to the upper operating system and programs. Thus, it is applicable to legacy code. Because of good code locality of the executable programs and effectiveness of branch prediction, the frequency of control-flow validations against the secure off-chip memory is low. Our experimental results show a negligible performance penalty and small storage overhead.<br /> <br /> <br /> == Motivation ==<br /> <br /> == People ==<br /> <br /> * [[Juan Carlos Martinez Santos]]<br /> <br /> == Publications ==<br /> <br /> *J. C. Martinez Santos and Y. Fei, “Leveraging speculative architectures for run-time program validation,” in Proc. IEEE Int. Conf. Computer Design, Oct. 2008.</div>

Jcmartinez http://nueess.coe.neu.edu/nueess/index.php/Anomalous_Path_Detection 2012-03-28T18:03:52Z

<p>Jcmartinez:&#32;/* Abstract */</p> <hr /> <div>== Overview ==<br /> <br /> Program execution can be tampered by malicious attackers through exploiting software vulnerabilities. Changing the program behavior by compromising control data and decision data has become the most serious threat in computer system security. Although several hardware approaches have been presented to validate program execution, they either incur great hardware overhead or introduce false alarms. <br /> <br /> We propose a new hardware-based approach by leveraging the existing speculative architectures for run-time program validation. The on-chip branch target buffer (BTB) is utilized as a cache of the legitimate control flow transfers stored in a secure memory region. In addition, the BTB is extended to store the correct program path information. At each indirect branch site, the BTB is used to validate the decision history of previous conditional branches and monitor the following execution path at run-time. <br /> <br /> Implementation of this approach is transparent to the upper operating system and programs. Thus, it is applicable to legacy code. Because of good code locality of the executable programs and effectiveness of branch prediction, the frequency of control-flow validations against the secure off-chip memory is low. Our experimental results show a negligible performance penalty and small storage overhead.<br /> <br /> == People ==<br /> <br /> * [[Juan Carlos Martinez Santos]]<br /> <br /> == Publications ==<br /> <br /> *J. C. Martinez Santos and Y. Fei, “Leveraging speculative architectures for run-time program validation,” in Proc. IEEE Int. Conf. Computer Design, Oct. 2008.</div>

Jcmartinez http://nueess.coe.neu.edu/nueess/index.php/Anomalous_Path_Detection 2012-03-28T18:03:27Z

<p>Jcmartinez:&#32;/* Publications */</p> <hr /> <div>== Abstract ==<br /> <br /> Program execution can be tampered by malicious attackers through exploiting software vulnerabilities. Changing the program behavior by compromising control data and decision data has become the most serious threat in computer system security. Although several hardware approaches have been presented to validate program execution, they either incur great hardware overhead or introduce false alarms. <br /> <br /> We propose a new hardware-based approach by leveraging the existing speculative architectures for run-time program validation. The on-chip branch target buffer (BTB) is utilized as a cache of the legitimate control flow transfers stored in a secure memory region. In addition, the BTB is extended to store the correct program path information. At each indirect branch site, the BTB is used to validate the decision history of previous conditional branches and monitor the following execution path at run-time. <br /> <br /> Implementation of this approach is transparent to the upper operating system and programs. Thus, it is applicable to legacy code. Because of good code locality of the executable programs and effectiveness of branch prediction, the frequency of control-flow validations against the secure off-chip memory is low. Our experimental results show a negligible performance penalty and small storage overhead.<br /> <br /> <br /> == People ==<br /> <br /> * [[Juan Carlos Martinez Santos]]<br /> <br /> == Publications ==<br /> <br /> *J. C. Martinez Santos and Y. Fei, “Leveraging speculative architectures for run-time program validation,” in Proc. IEEE Int. Conf. Computer Design, Oct. 2008.</div>

Jcmartinez http://nueess.coe.neu.edu/nueess/index.php/Anomalous_Path_Detection 2012-03-28T18:02:54Z

<p>Jcmartinez:&#32;/* People */</p> <hr /> <div>== Abstract ==<br /> <br /> Program execution can be tampered by malicious attackers through exploiting software vulnerabilities. Changing the program behavior by compromising control data and decision data has become the most serious threat in computer system security. Although several hardware approaches have been presented to validate program execution, they either incur great hardware overhead or introduce false alarms. <br /> <br /> We propose a new hardware-based approach by leveraging the existing speculative architectures for run-time program validation. The on-chip branch target buffer (BTB) is utilized as a cache of the legitimate control flow transfers stored in a secure memory region. In addition, the BTB is extended to store the correct program path information. At each indirect branch site, the BTB is used to validate the decision history of previous conditional branches and monitor the following execution path at run-time. <br /> <br /> Implementation of this approach is transparent to the upper operating system and programs. Thus, it is applicable to legacy code. Because of good code locality of the executable programs and effectiveness of branch prediction, the frequency of control-flow validations against the secure off-chip memory is low. Our experimental results show a negligible performance penalty and small storage overhead.<br /> <br /> <br /> == People ==<br /> <br /> * [[Juan Carlos Martinez Santos]]<br /> <br /> == Publications ==</div>

Jcmartinez http://nueess.coe.neu.edu/nueess/index.php/Anomalous_Path_Detection 2012-03-28T18:02:30Z

<p>Jcmartinez:&#32;/* Abstract */</p> <hr /> <div>== Abstract ==<br /> <br /> Program execution can be tampered by malicious attackers through exploiting software vulnerabilities. Changing the program behavior by compromising control data and decision data has become the most serious threat in computer system security. Although several hardware approaches have been presented to validate program execution, they either incur great hardware overhead or introduce false alarms. <br /> <br /> We propose a new hardware-based approach by leveraging the existing speculative architectures for run-time program validation. The on-chip branch target buffer (BTB) is utilized as a cache of the legitimate control flow transfers stored in a secure memory region. In addition, the BTB is extended to store the correct program path information. At each indirect branch site, the BTB is used to validate the decision history of previous conditional branches and monitor the following execution path at run-time. <br /> <br /> Implementation of this approach is transparent to the upper operating system and programs. Thus, it is applicable to legacy code. Because of good code locality of the executable programs and effectiveness of branch prediction, the frequency of control-flow validations against the secure off-chip memory is low. Our experimental results show a negligible performance penalty and small storage overhead.<br /> <br /> <br /> == People ==<br /> <br /> == Publications ==</div>

Jcmartinez http://nueess.coe.neu.edu/nueess/index.php/Multi-thread_isolation 2012-03-28T17:58:55Z

<p>Jcmartinez:&#32;Created page with &quot;== Abstract ==&quot;</p> <hr /> <div>== Abstract ==</div>

Jcmartinez http://nueess.coe.neu.edu/nueess/index.php/Hardware-assisted_Security 2012-03-28T17:58:42Z

<p>Jcmartinez:&#32;/* Projects */</p> <hr /> <div>='''Description'''=<br /> <br /> As networking connections become pervasive for computer systems and embedded software contents increase dramatically, it becomes more convenient for hostile parties to utilize software vulnerability to attack embedded systems, such as personal digital assistants (PDAs), cell phones, networked sensors, and automotive electronics. <br /> <br /> The vulnerability of embedded systems carrying sensitive information to security attacks, ranging from common cybercrimes to terrorism, has become a very critical problem with far-reaching financial and social implications. For example, security is still the largest concern that prevents the adoption of mobile commence and secure messaging. In addition to the traditional metrics of performance, area, and power consumption, security has been regarded as one of the most important design goals for networked embedded systems. <br /> <br /> Compared to the general purpose and commodity desktop system, an embedded system presents advantages in allowing deployment of meaningful countermeasures across system architecture design. Building a secure embedded system, however, is a complex task that requires multidisciplinary research across different system layers and spanning various design stages, including circuits, processors, Operating System (OS), compiler, system platform, etc. It is especially challenging to find efficient solutions granting system immunity to a broad range of evolving attacks, considering the stringent constraints of embedded systems on computing capability, memory, and battery power and the tamper-prone insecure environment.<br /> <br /> ='''Projects'''=<br /> *[[Multi-thread isolation]]<br /> *[[DIFT for multi-thread applications on multi-core architectures]]<br /> *[[Dynamic Information Flow Tracking]]<br /> *[[Anomalous Path Detection]]<br /> <br /> ='''People'''=<br /> <br /> * [[Juan Carlos Martinez Santos]]<br /> <br /> ='''Publications'''=<br /> '' Conference Papers ''<br /> *J. C. Martinez Santos, Y. Fei, and Z. J. Shi, “PIFT: Efficient dynamic information flow tracking using secure page allocation,” in WkShp on Embedded System Security (WESS) (held in conjunction with Embedded Systems Week), Oct. 2009.<br /> *J. C. Martinez Santos and Y. Fei, “Leveraging speculative architectures for run-time program validation,” in Proc. IEEE Int. Conf. Computer Design, Oct. 2008.</div>

Jcmartinez http://nueess.coe.neu.edu/nueess/index.php/Hardware-assisted_Security 2012-03-28T17:56:31Z

<p>Jcmartinez:&#32;</p> <hr /> <div>='''Description'''=<br /> <br /> As networking connections become pervasive for computer systems and embedded software contents increase dramatically, it becomes more convenient for hostile parties to utilize software vulnerability to attack embedded systems, such as personal digital assistants (PDAs), cell phones, networked sensors, and automotive electronics. <br /> <br /> The vulnerability of embedded systems carrying sensitive information to security attacks, ranging from common cybercrimes to terrorism, has become a very critical problem with far-reaching financial and social implications. For example, security is still the largest concern that prevents the adoption of mobile commence and secure messaging. In addition to the traditional metrics of performance, area, and power consumption, security has been regarded as one of the most important design goals for networked embedded systems. <br /> <br /> Compared to the general purpose and commodity desktop system, an embedded system presents advantages in allowing deployment of meaningful countermeasures across system architecture design. Building a secure embedded system, however, is a complex task that requires multidisciplinary research across different system layers and spanning various design stages, including circuits, processors, Operating System (OS), compiler, system platform, etc. It is especially challenging to find efficient solutions granting system immunity to a broad range of evolving attacks, considering the stringent constraints of embedded systems on computing capability, memory, and battery power and the tamper-prone insecure environment.<br /> <br /> ='''Projects'''=<br /> *[[DIFT for multi-thread applications on multi-core architectures]]<br /> *[[Dynamic Information Flow Tracking]]<br /> *[[Anomalous Path Detection]]<br /> <br /> ='''People'''=<br /> <br /> * [[Juan Carlos Martinez Santos]]<br /> <br /> ='''Publications'''=<br /> '' Conference Papers ''<br /> *J. C. Martinez Santos, Y. Fei, and Z. J. Shi, “PIFT: Efficient dynamic information flow tracking using secure page allocation,” in WkShp on Embedded System Security (WESS) (held in conjunction with Embedded Systems Week), Oct. 2009.<br /> *J. C. Martinez Santos and Y. Fei, “Leveraging speculative architectures for run-time program validation,” in Proc. IEEE Int. Conf. Computer Design, Oct. 2008.</div>

Jcmartinez http://nueess.coe.neu.edu/nueess/index.php/Hardware-assisted_Security 2012-03-28T17:52:43Z

<p>Jcmartinez:&#32;/* Description */</p> <hr /> <div>='''Description'''=<br /> As networking connections become pervasive for computer systems and embedded software contents increase dramatically, it becomes more convenient for hostile parties to utilize software vulnerability to attack embedded systems, such as personal digital assistants (PDAs), cell phones, networked sensors, and automotive electronics. <br /> <br /> The vulnerability of embedded systems carrying sensitive information to security attacks, ranging from common cybercrimes to terrorism, has become a very critical problem with far-reaching financial and social implications. For example, security is still the largest concern that prevents the adoption of mobile commence and secure messaging. In addition to the traditional metrics of performance, area, and power consumption, security has been regarded as one of the most important design goals for networked embedded systems. <br /> <br /> Compared to the general purpose and commodity desktop system, an embedded system presents advantages in allowing deployment of meaningful countermeasures across system architecture design. Building a secure embedded system, however, is a complex task that requires multidisciplinary research across different system layers and spanning various design stages, including circuits, processors, Operating System (OS), compiler, system platform, etc. It is especially challenging to find efficient solutions granting system immunity to a broad range of evolving attacks, considering the stringent constraints of embedded systems on computing capability, memory, and battery power and the tamper-prone insecure environment.<br /> <br /> ='''Projects'''=<br /> *[[DIFT for multi-thread applications on multi-core architectures]]<br /> *[[Dynamic Information Flow Tracking]]<br /> *[[Anomalous Path Detection]]<br /> <br /> ='''People'''=<br /> <br /> * [[Juan Carlos Martinez Santos]]<br /> <br /> ='''Publications'''=<br /> '' Conference Papers ''<br /> *J. C. Martinez Santos, Y. Fei, and Z. J. Shi, “PIFT: Efficient dynamic information flow tracking using secure page allocation,” in WkShp on Embedded System Security (WESS) (held in conjunction with Embedded Systems Week), Oct. 2009.<br /> *J. C. Martinez Santos and Y. Fei, “Leveraging speculative architectures for run-time program validation,” in Proc. IEEE Int. Conf. Computer Design, Oct. 2008.</div>

Jcmartinez http://nueess.coe.neu.edu/nueess/index.php/Juan_Carlos_Martinez_Santos 2012-03-28T17:40:10Z

<p>Jcmartinez:&#32;/* Education */</p> <hr /> <div>[[image:Juan-photo.jpg|thumb|200px|left]]<br /> '''Juan Carlos Martinez Santos'''<br /> <br /> Ph.D Candidate<br /> <br /> Department of Electrical and Computer Engineering<br /> <br /> Northeastern University<br /> <br /> Egan 227<br /> <br /> Boston, MA 02115, USA<br /> <br /> Email: martinezsantos.j AT husky.neu.edu<br /> <br /> Webpage: http://laurel.engr.uconn.edu/~jcmartin<br /> <br /> == Education ==<br /> *Ph.D. Candidate: [http://www.ece.neu.edu/ece Dept. of Electrical and Computer Engineering], [http://www.northeastern.edu/ Northeastern University], USA, 2012 (expected)<br /> :Advisor: [http://www.ece.neu.edu/ece/index.php/component/content/170?task=view Prof. Yunsi Fei]<br /> <br /> *M.Sc and B.S.: [http://www.uis.edu.co/webUIS/es/academia/facultades/fisicoMecanicas/escuelas/e3t/ Escuela de Ingenierias Electrica, Electronica y Telecomunicaciones], [http://www.uis.edu.co/webUIS/en/index.html Universidad Industrial de Santander], Bucaramanga, Santander - Colombia, 2004 - 2001<br /> :Advisor: Prof. Jorge Ramon<br /> <br /> == Research ==<br /> *[[DIFT for multi-thread applications on multi-core architectures]]<br /> *[[Dynamic Information Flow Tracking]]<br /> *[[Anomalous Path Detection]]<br /> <br /> == Publications ==<br /> '' Journal Papers''<br /> *J. C. Martinez Santos, S. H. Contreras Ortiz, “Tele-operated Laboratory for Digital Systems Design” (Original Title: Laboratorio Tele-operado de Técnicas Digitales), in Revista Colombiana De Tecnologías De Avanzada, ISSN: 1692-7257 ed: Java Eu v.6 fasc. p.92 – 96. Colombia, 2005 – Language: Spanish<br /> *J. C. Martinez Santos, J. H. Ramon Suarez, “Teaching Digital Systems Design using Hardware Description Languages” (Original Title: Enseñanza de Sistemas Digitales usando lenguajes de descripción de hardware), in UIS Ingenierías ISSN: 1657-4583 ed: Publicaciones UIS v.2 fasc.1 p.35 – 39. Colombia ,2003 – Language: Spanish<br /> <br /> '' Conference Papers ''<br /> *J. C. Martinez Santos, Y. Fei, and Z. J. Shi, “PIFT: Efficient dynamic information flow tracking using secure page allocation,” in WkShp on Embedded System Security (WESS) (held in conjunction with Embedded Systems Week), Oct. 2009.<br /> *J. C. Martinez Santos and Y. Fei, “Leveraging speculative architectures for run-time program validation,” in Proc. IEEE Int. Conf. Computer Design, Oct. 2008.<br /> *J. C. Martinez Santos, L. S. Silva Lopez, “A Platform for Developing Skills on Implementation of Wireless Sensor Networks Using Active Learning”, in Active Learning on Engineering, Universidad de Los Andes, p.205 - 206, Bogota, Colombia, 2008<br /> *J. C. Martinez Santos, L. S. Silva Lopez, O. G. Erazo Cruz, “A Study Case: a WSN using IEE and MAC SMAC hardware with adjustable duty cycle for improving battery life time” (Original Title: El caso de una WSN empleando Hardware IEE y MAC SMAC, con variación de ciclos de trabajo para mejorar vida de Baterías), in Proc. i2ComM . ISBN: 9789588375 ed: I2COMM, p.122 - 127, Colombia 2008 – Language: Spanish<br /> *J. C. Martinez Santos, L. S. Silva Lopez, E. Ospina Mateus, “Analysis of a WSN inside of a car using the IEEE 802.15.4 standard with adjustable duty cycle for improving battery life time” (Original Title: Análisis de una WSN en un Automóvil bajo IEEE 802.15.4 con Variación de Ciclos de Trabajo para Mejorar Vida de Baterías), in IEEE Colcom 2007, Congreso Colombiano De Comunicaciones . ISBN: 978-958-44, Colombia, 2007 – Language: Spanish<br /> *J. C. Martinez Santos, S. H. Contreras Ortiz, E. Gomez Vasquez, O. Acevedo Patiño, “LABTO: Teleoperated Laboratory of Digital Systems Design” (Original Title: LABTO: Laboratorio TeleOperado de Tecnicas Digitales), in IEEE Colombian Workshop on Circuits and Systems , ISBN: 978-958-69 ed: Universidad De Los Andes. Colombia, 2006 – Language: Spanish<br /> *J. C. Martinez Santos, O. S. Bayter Fontalvo, “Total Harmonic Distortion meter using a Digital Signal Processor” (Original Title: Medidor de Distorsión Armónica Total basado en un Procesador Digital de Señales), in XI Simposio de Tratamiento de Señales, Imagenes y vision Artificial. . ISBN: 958-683-93 ed: Sociedad Colombiana de Tratamiento de Señales , v. I. Colombia, 2006 – Language: Spanish<br /> *J. C. Martinez Santos, S. H. Contreras Ortiz, E. Gomez Vasquez, O. Acevedo Patiño, “Tele-operated laboratory of Digital systems Desing” (Original Title: Laboratorio Tele-operado de Técnicas Digitales), in XXIV Reunión Nacional de Facultades de Ingeniería. ISBN: 958-608-049-8, p.195 – 199. Colombia, 2004 – Language: Spanish<br /> <br /> '' Books ''<br /> *J. C. Martinez Santos, J. Duque, “A text book for Digital Circuits” (Original Title: Circuitos Digitales). ed: Ediciones Tecnologica de Bolivar ISBN: 9589745946 v. 1 pages. 143. Colombia, 2004 – Language: Spanish</div>

Jcmartinez http://nueess.coe.neu.edu/nueess/index.php/Juan_Carlos_Martinez_Santos 2012-03-28T17:39:26Z

<p>Jcmartinez:&#32;</p> <hr /> <div>[[image:Juan-photo.jpg|thumb|200px|left]]<br /> '''Juan Carlos Martinez Santos'''<br /> <br /> Ph.D Candidate<br /> <br /> Department of Electrical and Computer Engineering<br /> <br /> Northeastern University<br /> <br /> Egan 227<br /> <br /> Boston, MA 02115, USA<br /> <br /> Email: martinezsantos.j AT husky.neu.edu<br /> <br /> Webpage: http://laurel.engr.uconn.edu/~jcmartin<br /> <br /> == Education ==<br /> *Ph.D. Candidate: [http://www.ece.neu.edu/ece Dept. of Electrical and Computer Engineering], [http://www.northeastern.edu/ Northeastern University], USA, 2012 (expected)<br /> :Advisor: [http://www.ece.neu.edu/ece/index.php/component/content/170?task=view Prof. Yunsi Fei]<br /> <br /> *M.Sc and B.S.: [http://www.uis.edu.co/webUIS/es/academia/facultades/fisicoMecanicas/escuelas/e3t/ Escuela de Ingenierias Electrica, Electronica y Telecomunicaciones], [http://www.uis.edu.co/webUIS/en/index.html Universidad Industrial de Santander], Bucaramanga, Santander - Colombia, 2004 - 2001<br /> <br /> == Research ==<br /> *[[DIFT for multi-thread applications on multi-core architectures]]<br /> *[[Dynamic Information Flow Tracking]]<br /> *[[Anomalous Path Detection]]<br /> <br /> == Publications ==<br /> '' Journal Papers''<br /> *J. C. Martinez Santos, S. H. Contreras Ortiz, “Tele-operated Laboratory for Digital Systems Design” (Original Title: Laboratorio Tele-operado de Técnicas Digitales), in Revista Colombiana De Tecnologías De Avanzada, ISSN: 1692-7257 ed: Java Eu v.6 fasc. p.92 – 96. Colombia, 2005 – Language: Spanish<br /> *J. C. Martinez Santos, J. H. Ramon Suarez, “Teaching Digital Systems Design using Hardware Description Languages” (Original Title: Enseñanza de Sistemas Digitales usando lenguajes de descripción de hardware), in UIS Ingenierías ISSN: 1657-4583 ed: Publicaciones UIS v.2 fasc.1 p.35 – 39. Colombia ,2003 – Language: Spanish<br /> <br /> '' Conference Papers ''<br /> *J. C. Martinez Santos, Y. Fei, and Z. J. Shi, “PIFT: Efficient dynamic information flow tracking using secure page allocation,” in WkShp on Embedded System Security (WESS) (held in conjunction with Embedded Systems Week), Oct. 2009.<br /> *J. C. Martinez Santos and Y. Fei, “Leveraging speculative architectures for run-time program validation,” in Proc. IEEE Int. Conf. Computer Design, Oct. 2008.<br /> *J. C. Martinez Santos, L. S. Silva Lopez, “A Platform for Developing Skills on Implementation of Wireless Sensor Networks Using Active Learning”, in Active Learning on Engineering, Universidad de Los Andes, p.205 - 206, Bogota, Colombia, 2008<br /> *J. C. Martinez Santos, L. S. Silva Lopez, O. G. Erazo Cruz, “A Study Case: a WSN using IEE and MAC SMAC hardware with adjustable duty cycle for improving battery life time” (Original Title: El caso de una WSN empleando Hardware IEE y MAC SMAC, con variación de ciclos de trabajo para mejorar vida de Baterías), in Proc. i2ComM . ISBN: 9789588375 ed: I2COMM, p.122 - 127, Colombia 2008 – Language: Spanish<br /> *J. C. Martinez Santos, L. S. Silva Lopez, E. Ospina Mateus, “Analysis of a WSN inside of a car using the IEEE 802.15.4 standard with adjustable duty cycle for improving battery life time” (Original Title: Análisis de una WSN en un Automóvil bajo IEEE 802.15.4 con Variación de Ciclos de Trabajo para Mejorar Vida de Baterías), in IEEE Colcom 2007, Congreso Colombiano De Comunicaciones . ISBN: 978-958-44, Colombia, 2007 – Language: Spanish<br /> *J. C. Martinez Santos, S. H. Contreras Ortiz, E. Gomez Vasquez, O. Acevedo Patiño, “LABTO: Teleoperated Laboratory of Digital Systems Design” (Original Title: LABTO: Laboratorio TeleOperado de Tecnicas Digitales), in IEEE Colombian Workshop on Circuits and Systems , ISBN: 978-958-69 ed: Universidad De Los Andes. Colombia, 2006 – Language: Spanish<br /> *J. C. Martinez Santos, O. S. Bayter Fontalvo, “Total Harmonic Distortion meter using a Digital Signal Processor” (Original Title: Medidor de Distorsión Armónica Total basado en un Procesador Digital de Señales), in XI Simposio de Tratamiento de Señales, Imagenes y vision Artificial. . ISBN: 958-683-93 ed: Sociedad Colombiana de Tratamiento de Señales , v. I. Colombia, 2006 – Language: Spanish<br /> *J. C. Martinez Santos, S. H. Contreras Ortiz, E. Gomez Vasquez, O. Acevedo Patiño, “Tele-operated laboratory of Digital systems Desing” (Original Title: Laboratorio Tele-operado de Técnicas Digitales), in XXIV Reunión Nacional de Facultades de Ingeniería. ISBN: 958-608-049-8, p.195 – 199. Colombia, 2004 – Language: Spanish<br /> <br /> '' Books ''<br /> *J. C. Martinez Santos, J. Duque, “A text book for Digital Circuits” (Original Title: Circuitos Digitales). ed: Ediciones Tecnologica de Bolivar ISBN: 9589745946 v. 1 pages. 143. Colombia, 2004 – Language: Spanish</div>

Jcmartinez http://nueess.coe.neu.edu/nueess/index.php/Juan_Carlos_Martinez_Santos 2012-03-28T17:38:59Z

<p>Jcmartinez:&#32;</p> <hr /> <div>[[image:Juan-photo.jpg|thumb|200px|left]]<br /> '''Juan Carlos Martinez Santos'''<br /> <br /> Ph.D Candidate<br /> <br /> Department of Electrical and Computer Engineering<br /> <br /> Northeastern University<br /> <br /> Egan 227<br /> <br /> Boston, MA 02115, USA<br /> <br /> Email: martinezsantos.j AT engr.uconn.edu<br /> <br /> Webpage: http://laurel.engr.uconn.edu/~jcmartin<br /> <br /> == Education ==<br /> *Ph.D. Candidate: [http://www.ece.neu.edu/ece Dept. of Electrical and Computer Engineering], [http://www.northeastern.edu/ Northeastern University], USA, 2012 (expected)<br /> :Advisor: [http://www.ece.neu.edu/ece/index.php/component/content/170?task=view Prof. Yunsi Fei]<br /> <br /> *M.Sc and B.S.: [http://www.uis.edu.co/webUIS/es/academia/facultades/fisicoMecanicas/escuelas/e3t/ Escuela de Ingenierias Electrica, Electronica y Telecomunicaciones], [http://www.uis.edu.co/webUIS/en/index.html Universidad Industrial de Santander], Bucaramanga, Santander - Colombia, 2004 - 2001<br /> <br /> == Research ==<br /> *[[DIFT for multi-thread applications on multi-core architectures]]<br /> *[[Dynamic Information Flow Tracking]]<br /> *[[Anomalous Path Detection]]<br /> <br /> == Publications ==<br /> '' Journal Papers''<br /> *J. C. Martinez Santos, S. H. Contreras Ortiz, “Tele-operated Laboratory for Digital Systems Design” (Original Title: Laboratorio Tele-operado de Técnicas Digitales), in Revista Colombiana De Tecnologías De Avanzada, ISSN: 1692-7257 ed: Java Eu v.6 fasc. p.92 – 96. Colombia, 2005 – Language: Spanish<br /> *J. C. Martinez Santos, J. H. Ramon Suarez, “Teaching Digital Systems Design using Hardware Description Languages” (Original Title: Enseñanza de Sistemas Digitales usando lenguajes de descripción de hardware), in UIS Ingenierías ISSN: 1657-4583 ed: Publicaciones UIS v.2 fasc.1 p.35 – 39. Colombia ,2003 – Language: Spanish<br /> <br /> '' Conference Papers ''<br /> *J. C. Martinez Santos, Y. Fei, and Z. J. Shi, “PIFT: Efficient dynamic information flow tracking using secure page allocation,” in WkShp on Embedded System Security (WESS) (held in conjunction with Embedded Systems Week), Oct. 2009.<br /> *J. C. Martinez Santos and Y. Fei, “Leveraging speculative architectures for run-time program validation,” in Proc. IEEE Int. Conf. Computer Design, Oct. 2008.<br /> *J. C. Martinez Santos, L. S. Silva Lopez, “A Platform for Developing Skills on Implementation of Wireless Sensor Networks Using Active Learning”, in Active Learning on Engineering, Universidad de Los Andes, p.205 - 206, Bogota, Colombia, 2008<br /> *J. C. Martinez Santos, L. S. Silva Lopez, O. G. Erazo Cruz, “A Study Case: a WSN using IEE and MAC SMAC hardware with adjustable duty cycle for improving battery life time” (Original Title: El caso de una WSN empleando Hardware IEE y MAC SMAC, con variación de ciclos de trabajo para mejorar vida de Baterías), in Proc. i2ComM . ISBN: 9789588375 ed: I2COMM, p.122 - 127, Colombia 2008 – Language: Spanish<br /> *J. C. Martinez Santos, L. S. Silva Lopez, E. Ospina Mateus, “Analysis of a WSN inside of a car using the IEEE 802.15.4 standard with adjustable duty cycle for improving battery life time” (Original Title: Análisis de una WSN en un Automóvil bajo IEEE 802.15.4 con Variación de Ciclos de Trabajo para Mejorar Vida de Baterías), in IEEE Colcom 2007, Congreso Colombiano De Comunicaciones . ISBN: 978-958-44, Colombia, 2007 – Language: Spanish<br /> *J. C. Martinez Santos, S. H. Contreras Ortiz, E. Gomez Vasquez, O. Acevedo Patiño, “LABTO: Teleoperated Laboratory of Digital Systems Design” (Original Title: LABTO: Laboratorio TeleOperado de Tecnicas Digitales), in IEEE Colombian Workshop on Circuits and Systems , ISBN: 978-958-69 ed: Universidad De Los Andes. Colombia, 2006 – Language: Spanish<br /> *J. C. Martinez Santos, O. S. Bayter Fontalvo, “Total Harmonic Distortion meter using a Digital Signal Processor” (Original Title: Medidor de Distorsión Armónica Total basado en un Procesador Digital de Señales), in XI Simposio de Tratamiento de Señales, Imagenes y vision Artificial. . ISBN: 958-683-93 ed: Sociedad Colombiana de Tratamiento de Señales , v. I. Colombia, 2006 – Language: Spanish<br /> *J. C. Martinez Santos, S. H. Contreras Ortiz, E. Gomez Vasquez, O. Acevedo Patiño, “Tele-operated laboratory of Digital systems Desing” (Original Title: Laboratorio Tele-operado de Técnicas Digitales), in XXIV Reunión Nacional de Facultades de Ingeniería. ISBN: 958-608-049-8, p.195 – 199. Colombia, 2004 – Language: Spanish<br /> <br /> '' Books ''<br /> *J. C. Martinez Santos, J. Duque, “A text book for Digital Circuits” (Original Title: Circuitos Digitales). ed: Ediciones Tecnologica de Bolivar ISBN: 9589745946 v. 1 pages. 143. Colombia, 2004 – Language: Spanish</div>

Jcmartinez http://nueess.coe.neu.edu/nueess/index.php/Hardware-assisted_Security 2012-03-28T17:37:26Z

<p>Jcmartinez:&#32;/* Publications */</p> <hr /> <div>='''Description'''=<br /> ='''Projects'''=<br /> *[[DIFT for multi-thread applications on multi-core architectures]]<br /> *[[Dynamic Information Flow Tracking]]<br /> *[[Anomalous Path Detection]]<br /> <br /> ='''People'''=<br /> <br /> * [[Juan Carlos Martinez Santos]]<br /> <br /> ='''Publications'''=<br /> '' Conference Papers ''<br /> *J. C. Martinez Santos, Y. Fei, and Z. J. Shi, “PIFT: Efficient dynamic information flow tracking using secure page allocation,” in WkShp on Embedded System Security (WESS) (held in conjunction with Embedded Systems Week), Oct. 2009.<br /> *J. C. Martinez Santos and Y. Fei, “Leveraging speculative architectures for run-time program validation,” in Proc. IEEE Int. Conf. Computer Design, Oct. 2008.</div>

Jcmartinez http://nueess.coe.neu.edu/nueess/index.php/Hardware-assisted_Security 2012-03-28T17:36:40Z

<p>Jcmartinez:&#32;/* Projects */</p> <hr /> <div>='''Description'''=<br /> ='''Projects'''=<br /> *[[DIFT for multi-thread applications on multi-core architectures]]<br /> *[[Dynamic Information Flow Tracking]]<br /> *[[Anomalous Path Detection]]<br /> <br /> ='''People'''=<br /> <br /> * [[Juan Carlos Martinez Santos]]<br /> <br /> ='''Publications'''=</div>

Jcmartinez http://nueess.coe.neu.edu/nueess/index.php/Hardware-assisted_Security 2012-03-28T17:36:04Z

<p>Jcmartinez:&#32;</p> <hr /> <div>='''Description'''=<br /> ='''Projects'''=<br /> ='''People'''=<br /> <br /> * [[Juan Carlos Martinez Santos]]<br /> <br /> ='''Publications'''=</div>

Jcmartinez http://nueess.coe.neu.edu/nueess/index.php/Hardware-assisted_Security 2012-03-28T17:34:00Z

<p>Jcmartinez:&#32;/* People */</p> <hr /> <div>='''Description'''=<br /> ='''People'''=<br /> <br /> * [[Juan Carlos Martinez Santos]]<br /> <br /> ='''Publications'''=</div>

Jcmartinez http://nueess.coe.neu.edu/nueess/index.php/Anomalous_Path_Detection 2012-03-28T17:32:58Z

<p>Jcmartinez:&#32;/* Abstract */</p> <hr /> <div>== Abstract ==<br /> <br /> Program execution can be tampered by malicious attackers through exploiting software vulnerabilities. Changing the program behavior by compromising control data and decision data has become the most serious threat in computer system security. Although several hardware approaches have been presented to validate program execution, they either incur great hardware overhead or introduce false alarms. <br /> <br /> We propose a new hardware-based approach by leveraging the existing speculative architectures for run-time program validation. The on-chip branch target buffer (BTB) is utilized as a cache of the legitimate control flow transfers stored in a secure memory region. In addition, the BTB is extended to store the correct program path information. At each indirect branch site, the BTB is used to validate the decision history of previous conditional branches and monitor the following execution path at run-time. <br /> <br /> Implementation of this approach is transparent to the upper operating system and programs. Thus, it is applicable to legacy code. Because of good code locality of the executable programs and effectiveness of branch prediction, the frequency of control-flow validations against the secure off-chip memory is low. Our experimental results show a negligible performance penalty and small storage overhead.</div>

Jcmartinez http://nueess.coe.neu.edu/nueess/index.php/Juan_Carlos_Martinez_Santos 2012-03-28T17:30:59Z

<p>Jcmartinez:&#32;/* Research */</p> <hr /> <div>[[image:Juan-photo.jpg|thumb|200px|left]]<br /> '''Juan Carlos Martinez Santos'''<br /> <br /> Ph.D Candidate<br /> <br /> Department of Electrical and Computer Engineering<br /> <br /> University of Connecticut<br /> <br /> 371 Fairfield Way, U-2157<br /> <br /> Storrs, CT 06269-2157, USA<br /> <br /> Email: jsm07006 AT engr.uconn.edu<br /> <br /> Webpage: http://laurel.engr.uconn.edu/~jcmartin<br /> <br /> == Education ==<br /> *Ph.D. Candidate: [http://www.ece.neu.edu/ece Dept. of Electrical and Computer Engineering], [http://www.northeastern.edu/ Northeastern University], USA, 2012 (expected)<br /> :Advisor: [http://www.ece.neu.edu/ece/index.php/component/content/170?task=view Prof. Yunsi Fei]<br /> <br /> *M.Sc and B.S.: [http://www.uis.edu.co/webUIS/es/academia/facultades/fisicoMecanicas/escuelas/e3t/ Escuela de Ingenierias Electrica, Electronica y Telecomunicaciones], [http://www.uis.edu.co/webUIS/en/index.html Universidad Industrial de Santander], Bucaramanga, Santander - Colombia, 2004 - 2001<br /> <br /> == Research ==<br /> *[[DIFT for multi-thread applications on multi-core architectures]]<br /> *[[Dynamic Information Flow Tracking]]<br /> *[[Anomalous Path Detection]]<br /> <br /> == Publications ==<br /> '' Journal Papers''<br /> *J. C. Martinez Santos, S. H. Contreras Ortiz, “Tele-operated Laboratory for Digital Systems Design” (Original Title: Laboratorio Tele-operado de Técnicas Digitales), in Revista Colombiana De Tecnologías De Avanzada, ISSN: 1692-7257 ed: Java Eu v.6 fasc. p.92 – 96. Colombia, 2005 – Language: Spanish<br /> *J. C. Martinez Santos, J. H. Ramon Suarez, “Teaching Digital Systems Design using Hardware Description Languages” (Original Title: Enseñanza de Sistemas Digitales usando lenguajes de descripción de hardware), in UIS Ingenierías ISSN: 1657-4583 ed: Publicaciones UIS v.2 fasc.1 p.35 – 39. Colombia ,2003 – Language: Spanish<br /> <br /> '' Conference Papers ''<br /> *J. C. Martinez Santos, Y. Fei, and Z. J. Shi, “PIFT: Efficient dynamic information flow tracking using secure page allocation,” in WkShp on Embedded System Security (WESS) (held in conjunction with Embedded Systems Week), Oct. 2009.<br /> *J. C. Martinez Santos and Y. Fei, “Leveraging speculative architectures for run-time program validation,” in Proc. IEEE Int. Conf. Computer Design, Oct. 2008.<br /> *J. C. Martinez Santos, L. S. Silva Lopez, “A Platform for Developing Skills on Implementation of Wireless Sensor Networks Using Active Learning”, in Active Learning on Engineering, Universidad de Los Andes, p.205 - 206, Bogota, Colombia, 2008<br /> *J. C. Martinez Santos, L. S. Silva Lopez, O. G. Erazo Cruz, “A Study Case: a WSN using IEE and MAC SMAC hardware with adjustable duty cycle for improving battery life time” (Original Title: El caso de una WSN empleando Hardware IEE y MAC SMAC, con variación de ciclos de trabajo para mejorar vida de Baterías), in Proc. i2ComM . ISBN: 9789588375 ed: I2COMM, p.122 - 127, Colombia 2008 – Language: Spanish<br /> *J. C. Martinez Santos, L. S. Silva Lopez, E. Ospina Mateus, “Analysis of a WSN inside of a car using the IEEE 802.15.4 standard with adjustable duty cycle for improving battery life time” (Original Title: Análisis de una WSN en un Automóvil bajo IEEE 802.15.4 con Variación de Ciclos de Trabajo para Mejorar Vida de Baterías), in IEEE Colcom 2007, Congreso Colombiano De Comunicaciones . ISBN: 978-958-44, Colombia, 2007 – Language: Spanish<br /> *J. C. Martinez Santos, S. H. Contreras Ortiz, E. Gomez Vasquez, O. Acevedo Patiño, “LABTO: Teleoperated Laboratory of Digital Systems Design” (Original Title: LABTO: Laboratorio TeleOperado de Tecnicas Digitales), in IEEE Colombian Workshop on Circuits and Systems , ISBN: 978-958-69 ed: Universidad De Los Andes. Colombia, 2006 – Language: Spanish<br /> *J. C. Martinez Santos, O. S. Bayter Fontalvo, “Total Harmonic Distortion meter using a Digital Signal Processor” (Original Title: Medidor de Distorsión Armónica Total basado en un Procesador Digital de Señales), in XI Simposio de Tratamiento de Señales, Imagenes y vision Artificial. . ISBN: 958-683-93 ed: Sociedad Colombiana de Tratamiento de Señales , v. I. Colombia, 2006 – Language: Spanish<br /> *J. C. Martinez Santos, S. H. Contreras Ortiz, E. Gomez Vasquez, O. Acevedo Patiño, “Tele-operated laboratory of Digital systems Desing” (Original Title: Laboratorio Tele-operado de Técnicas Digitales), in XXIV Reunión Nacional de Facultades de Ingeniería. ISBN: 958-608-049-8, p.195 – 199. Colombia, 2004 – Language: Spanish<br /> <br /> '' Books ''<br /> *J. C. Martinez Santos, J. Duque, “A text book for Digital Circuits” (Original Title: Circuitos Digitales). ed: Ediciones Tecnologica de Bolivar ISBN: 9589745946 v. 1 pages. 143. Colombia, 2004 – Language: Spanish</div>

Jcmartinez http://nueess.coe.neu.edu/nueess/index.php/Juan_Carlos_Martinez_Santos 2012-03-28T17:30:28Z

<p>Jcmartinez:&#32;/* Research */</p> <hr /> <div>[[image:Juan-photo.jpg|thumb|200px|left]]<br /> '''Juan Carlos Martinez Santos'''<br /> <br /> Ph.D Candidate<br /> <br /> Department of Electrical and Computer Engineering<br /> <br /> University of Connecticut<br /> <br /> 371 Fairfield Way, U-2157<br /> <br /> Storrs, CT 06269-2157, USA<br /> <br /> Email: jsm07006 AT engr.uconn.edu<br /> <br /> Webpage: http://laurel.engr.uconn.edu/~jcmartin<br /> <br /> == Education ==<br /> *Ph.D. Candidate: [http://www.ece.neu.edu/ece Dept. of Electrical and Computer Engineering], [http://www.northeastern.edu/ Northeastern University], USA, 2012 (expected)<br /> :Advisor: [http://www.ece.neu.edu/ece/index.php/component/content/170?task=view Prof. Yunsi Fei]<br /> <br /> *M.Sc and B.S.: [http://www.uis.edu.co/webUIS/es/academia/facultades/fisicoMecanicas/escuelas/e3t/ Escuela de Ingenierias Electrica, Electronica y Telecomunicaciones], [http://www.uis.edu.co/webUIS/en/index.html Universidad Industrial de Santander], Bucaramanga, Santander - Colombia, 2004 - 2001<br /> <br /> == Research ==<br /> *[DIFT for multi-thread applications on multi-core architectures]<br /> *[Dynamic Information Flow Tracking]<br /> *[[Anomalous Path Detection]] - tres<br /> <br /> == Publications ==<br /> '' Journal Papers''<br /> *J. C. Martinez Santos, S. H. Contreras Ortiz, “Tele-operated Laboratory for Digital Systems Design” (Original Title: Laboratorio Tele-operado de Técnicas Digitales), in Revista Colombiana De Tecnologías De Avanzada, ISSN: 1692-7257 ed: Java Eu v.6 fasc. p.92 – 96. Colombia, 2005 – Language: Spanish<br /> *J. C. Martinez Santos, J. H. Ramon Suarez, “Teaching Digital Systems Design using Hardware Description Languages” (Original Title: Enseñanza de Sistemas Digitales usando lenguajes de descripción de hardware), in UIS Ingenierías ISSN: 1657-4583 ed: Publicaciones UIS v.2 fasc.1 p.35 – 39. Colombia ,2003 – Language: Spanish<br /> <br /> '' Conference Papers ''<br /> *J. C. Martinez Santos, Y. Fei, and Z. J. Shi, “PIFT: Efficient dynamic information flow tracking using secure page allocation,” in WkShp on Embedded System Security (WESS) (held in conjunction with Embedded Systems Week), Oct. 2009.<br /> *J. C. Martinez Santos and Y. Fei, “Leveraging speculative architectures for run-time program validation,” in Proc. IEEE Int. Conf. Computer Design, Oct. 2008.<br /> *J. C. Martinez Santos, L. S. Silva Lopez, “A Platform for Developing Skills on Implementation of Wireless Sensor Networks Using Active Learning”, in Active Learning on Engineering, Universidad de Los Andes, p.205 - 206, Bogota, Colombia, 2008<br /> *J. C. Martinez Santos, L. S. Silva Lopez, O. G. Erazo Cruz, “A Study Case: a WSN using IEE and MAC SMAC hardware with adjustable duty cycle for improving battery life time” (Original Title: El caso de una WSN empleando Hardware IEE y MAC SMAC, con variación de ciclos de trabajo para mejorar vida de Baterías), in Proc. i2ComM . ISBN: 9789588375 ed: I2COMM, p.122 - 127, Colombia 2008 – Language: Spanish<br /> *J. C. Martinez Santos, L. S. Silva Lopez, E. Ospina Mateus, “Analysis of a WSN inside of a car using the IEEE 802.15.4 standard with adjustable duty cycle for improving battery life time” (Original Title: Análisis de una WSN en un Automóvil bajo IEEE 802.15.4 con Variación de Ciclos de Trabajo para Mejorar Vida de Baterías), in IEEE Colcom 2007, Congreso Colombiano De Comunicaciones . ISBN: 978-958-44, Colombia, 2007 – Language: Spanish<br /> *J. C. Martinez Santos, S. H. Contreras Ortiz, E. Gomez Vasquez, O. Acevedo Patiño, “LABTO: Teleoperated Laboratory of Digital Systems Design” (Original Title: LABTO: Laboratorio TeleOperado de Tecnicas Digitales), in IEEE Colombian Workshop on Circuits and Systems , ISBN: 978-958-69 ed: Universidad De Los Andes. Colombia, 2006 – Language: Spanish<br /> *J. C. Martinez Santos, O. S. Bayter Fontalvo, “Total Harmonic Distortion meter using a Digital Signal Processor” (Original Title: Medidor de Distorsión Armónica Total basado en un Procesador Digital de Señales), in XI Simposio de Tratamiento de Señales, Imagenes y vision Artificial. . ISBN: 958-683-93 ed: Sociedad Colombiana de Tratamiento de Señales , v. I. Colombia, 2006 – Language: Spanish<br /> *J. C. Martinez Santos, S. H. Contreras Ortiz, E. Gomez Vasquez, O. Acevedo Patiño, “Tele-operated laboratory of Digital systems Desing” (Original Title: Laboratorio Tele-operado de Técnicas Digitales), in XXIV Reunión Nacional de Facultades de Ingeniería. ISBN: 958-608-049-8, p.195 – 199. Colombia, 2004 – Language: Spanish<br /> <br /> '' Books ''<br /> *J. C. Martinez Santos, J. Duque, “A text book for Digital Circuits” (Original Title: Circuitos Digitales). ed: Ediciones Tecnologica de Bolivar ISBN: 9589745946 v. 1 pages. 143. Colombia, 2004 – Language: Spanish</div>

Jcmartinez http://nueess.coe.neu.edu/nueess/index.php/Juan_Carlos_Martinez_Santos 2012-03-28T17:27:14Z

<p>Jcmartinez:&#32;/* Research */</p> <hr /> <div>[[image:Juan-photo.jpg|thumb|200px|left]]<br /> '''Juan Carlos Martinez Santos'''<br /> <br /> Ph.D Candidate<br /> <br /> Department of Electrical and Computer Engineering<br /> <br /> University of Connecticut<br /> <br /> 371 Fairfield Way, U-2157<br /> <br /> Storrs, CT 06269-2157, USA<br /> <br /> Email: jsm07006 AT engr.uconn.edu<br /> <br /> Webpage: http://laurel.engr.uconn.edu/~jcmartin<br /> <br /> == Education ==<br /> *Ph.D. Candidate: [http://www.ece.neu.edu/ece Dept. of Electrical and Computer Engineering], [http://www.northeastern.edu/ Northeastern University], USA, 2012 (expected)<br /> :Advisor: [http://www.ece.neu.edu/ece/index.php/component/content/170?task=view Prof. Yunsi Fei]<br /> <br /> *M.Sc and B.S.: [http://www.uis.edu.co/webUIS/es/academia/facultades/fisicoMecanicas/escuelas/e3t/ Escuela de Ingenierias Electrica, Electronica y Telecomunicaciones], [http://www.uis.edu.co/webUIS/en/index.html Universidad Industrial de Santander], Bucaramanga, Santander - Colombia, 2004 - 2001<br /> <br /> == Research ==<br /> *[DIFT for multi-thread applications on multi-core architectures]<br /> *[Dynamic Information Flow Tracking]<br /> *Anomalous Path Detection<br /> <br /> == Publications ==<br /> '' Journal Papers''<br /> *J. C. Martinez Santos, S. H. Contreras Ortiz, “Tele-operated Laboratory for Digital Systems Design” (Original Title: Laboratorio Tele-operado de Técnicas Digitales), in Revista Colombiana De Tecnologías De Avanzada, ISSN: 1692-7257 ed: Java Eu v.6 fasc. p.92 – 96. Colombia, 2005 – Language: Spanish<br /> *J. C. Martinez Santos, J. H. Ramon Suarez, “Teaching Digital Systems Design using Hardware Description Languages” (Original Title: Enseñanza de Sistemas Digitales usando lenguajes de descripción de hardware), in UIS Ingenierías ISSN: 1657-4583 ed: Publicaciones UIS v.2 fasc.1 p.35 – 39. Colombia ,2003 – Language: Spanish<br /> <br /> '' Conference Papers ''<br /> *J. C. Martinez Santos, Y. Fei, and Z. J. Shi, “PIFT: Efficient dynamic information flow tracking using secure page allocation,” in WkShp on Embedded System Security (WESS) (held in conjunction with Embedded Systems Week), Oct. 2009.<br /> *J. C. Martinez Santos and Y. Fei, “Leveraging speculative architectures for run-time program validation,” in Proc. IEEE Int. Conf. Computer Design, Oct. 2008.<br /> *J. C. Martinez Santos, L. S. Silva Lopez, “A Platform for Developing Skills on Implementation of Wireless Sensor Networks Using Active Learning”, in Active Learning on Engineering, Universidad de Los Andes, p.205 - 206, Bogota, Colombia, 2008<br /> *J. C. Martinez Santos, L. S. Silva Lopez, O. G. Erazo Cruz, “A Study Case: a WSN using IEE and MAC SMAC hardware with adjustable duty cycle for improving battery life time” (Original Title: El caso de una WSN empleando Hardware IEE y MAC SMAC, con variación de ciclos de trabajo para mejorar vida de Baterías), in Proc. i2ComM . ISBN: 9789588375 ed: I2COMM, p.122 - 127, Colombia 2008 – Language: Spanish<br /> *J. C. Martinez Santos, L. S. Silva Lopez, E. Ospina Mateus, “Analysis of a WSN inside of a car using the IEEE 802.15.4 standard with adjustable duty cycle for improving battery life time” (Original Title: Análisis de una WSN en un Automóvil bajo IEEE 802.15.4 con Variación de Ciclos de Trabajo para Mejorar Vida de Baterías), in IEEE Colcom 2007, Congreso Colombiano De Comunicaciones . ISBN: 978-958-44, Colombia, 2007 – Language: Spanish<br /> *J. C. Martinez Santos, S. H. Contreras Ortiz, E. Gomez Vasquez, O. Acevedo Patiño, “LABTO: Teleoperated Laboratory of Digital Systems Design” (Original Title: LABTO: Laboratorio TeleOperado de Tecnicas Digitales), in IEEE Colombian Workshop on Circuits and Systems , ISBN: 978-958-69 ed: Universidad De Los Andes. Colombia, 2006 – Language: Spanish<br /> *J. C. Martinez Santos, O. S. Bayter Fontalvo, “Total Harmonic Distortion meter using a Digital Signal Processor” (Original Title: Medidor de Distorsión Armónica Total basado en un Procesador Digital de Señales), in XI Simposio de Tratamiento de Señales, Imagenes y vision Artificial. . ISBN: 958-683-93 ed: Sociedad Colombiana de Tratamiento de Señales , v. I. Colombia, 2006 – Language: Spanish<br /> *J. C. Martinez Santos, S. H. Contreras Ortiz, E. Gomez Vasquez, O. Acevedo Patiño, “Tele-operated laboratory of Digital systems Desing” (Original Title: Laboratorio Tele-operado de Técnicas Digitales), in XXIV Reunión Nacional de Facultades de Ingeniería. ISBN: 958-608-049-8, p.195 – 199. Colombia, 2004 – Language: Spanish<br /> <br /> '' Books ''<br /> *J. C. Martinez Santos, J. Duque, “A text book for Digital Circuits” (Original Title: Circuitos Digitales). ed: Ediciones Tecnologica de Bolivar ISBN: 9589745946 v. 1 pages. 143. Colombia, 2004 – Language: Spanish</div>

Jcmartinez http://nueess.coe.neu.edu/nueess/index.php/Juan_Carlos_Martinez_Santos 2012-03-28T17:26:06Z

<p>Jcmartinez:&#32;/* Education */</p> <hr /> <div>[[image:Juan-photo.jpg|thumb|200px|left]]<br /> '''Juan Carlos Martinez Santos'''<br /> <br /> Ph.D Candidate<br /> <br /> Department of Electrical and Computer Engineering<br /> <br /> University of Connecticut<br /> <br /> 371 Fairfield Way, U-2157<br /> <br /> Storrs, CT 06269-2157, USA<br /> <br /> Email: jsm07006 AT engr.uconn.edu<br /> <br /> Webpage: http://laurel.engr.uconn.edu/~jcmartin<br /> <br /> == Education ==<br /> *Ph.D. Candidate: [http://www.ece.neu.edu/ece Dept. of Electrical and Computer Engineering], [http://www.northeastern.edu/ Northeastern University], USA, 2012 (expected)<br /> :Advisor: [http://www.ece.neu.edu/ece/index.php/component/content/170?task=view Prof. Yunsi Fei]<br /> <br /> *M.Sc and B.S.: [http://www.uis.edu.co/webUIS/es/academia/facultades/fisicoMecanicas/escuelas/e3t/ Escuela de Ingenierias Electrica, Electronica y Telecomunicaciones], [http://www.uis.edu.co/webUIS/en/index.html Universidad Industrial de Santander], Bucaramanga, Santander - Colombia, 2004 - 2001<br /> <br /> == Research ==<br /> *[DIFT for multi-thread applications on multi-core architectures]<br /> *[Dynamic Information Flow Tracking]<br /> *[Anomalous Path Detection]<br /> <br /> == Publications ==<br /> '' Journal Papers''<br /> *J. C. Martinez Santos, S. H. Contreras Ortiz, “Tele-operated Laboratory for Digital Systems Design” (Original Title: Laboratorio Tele-operado de Técnicas Digitales), in Revista Colombiana De Tecnologías De Avanzada, ISSN: 1692-7257 ed: Java Eu v.6 fasc. p.92 – 96. Colombia, 2005 – Language: Spanish<br /> *J. C. Martinez Santos, J. H. Ramon Suarez, “Teaching Digital Systems Design using Hardware Description Languages” (Original Title: Enseñanza de Sistemas Digitales usando lenguajes de descripción de hardware), in UIS Ingenierías ISSN: 1657-4583 ed: Publicaciones UIS v.2 fasc.1 p.35 – 39. Colombia ,2003 – Language: Spanish<br /> <br /> '' Conference Papers ''<br /> *J. C. Martinez Santos, Y. Fei, and Z. J. Shi, “PIFT: Efficient dynamic information flow tracking using secure page allocation,” in WkShp on Embedded System Security (WESS) (held in conjunction with Embedded Systems Week), Oct. 2009.<br /> *J. C. Martinez Santos and Y. Fei, “Leveraging speculative architectures for run-time program validation,” in Proc. IEEE Int. Conf. Computer Design, Oct. 2008.<br /> *J. C. Martinez Santos, L. S. Silva Lopez, “A Platform for Developing Skills on Implementation of Wireless Sensor Networks Using Active Learning”, in Active Learning on Engineering, Universidad de Los Andes, p.205 - 206, Bogota, Colombia, 2008<br /> *J. C. Martinez Santos, L. S. Silva Lopez, O. G. Erazo Cruz, “A Study Case: a WSN using IEE and MAC SMAC hardware with adjustable duty cycle for improving battery life time” (Original Title: El caso de una WSN empleando Hardware IEE y MAC SMAC, con variación de ciclos de trabajo para mejorar vida de Baterías), in Proc. i2ComM . ISBN: 9789588375 ed: I2COMM, p.122 - 127, Colombia 2008 – Language: Spanish<br /> *J. C. Martinez Santos, L. S. Silva Lopez, E. Ospina Mateus, “Analysis of a WSN inside of a car using the IEEE 802.15.4 standard with adjustable duty cycle for improving battery life time” (Original Title: Análisis de una WSN en un Automóvil bajo IEEE 802.15.4 con Variación de Ciclos de Trabajo para Mejorar Vida de Baterías), in IEEE Colcom 2007, Congreso Colombiano De Comunicaciones . ISBN: 978-958-44, Colombia, 2007 – Language: Spanish<br /> *J. C. Martinez Santos, S. H. Contreras Ortiz, E. Gomez Vasquez, O. Acevedo Patiño, “LABTO: Teleoperated Laboratory of Digital Systems Design” (Original Title: LABTO: Laboratorio TeleOperado de Tecnicas Digitales), in IEEE Colombian Workshop on Circuits and Systems , ISBN: 978-958-69 ed: Universidad De Los Andes. Colombia, 2006 – Language: Spanish<br /> *J. C. Martinez Santos, O. S. Bayter Fontalvo, “Total Harmonic Distortion meter using a Digital Signal Processor” (Original Title: Medidor de Distorsión Armónica Total basado en un Procesador Digital de Señales), in XI Simposio de Tratamiento de Señales, Imagenes y vision Artificial. . ISBN: 958-683-93 ed: Sociedad Colombiana de Tratamiento de Señales , v. I. Colombia, 2006 – Language: Spanish<br /> *J. C. Martinez Santos, S. H. Contreras Ortiz, E. Gomez Vasquez, O. Acevedo Patiño, “Tele-operated laboratory of Digital systems Desing” (Original Title: Laboratorio Tele-operado de Técnicas Digitales), in XXIV Reunión Nacional de Facultades de Ingeniería. ISBN: 958-608-049-8, p.195 – 199. Colombia, 2004 – Language: Spanish<br /> <br /> '' Books ''<br /> *J. C. Martinez Santos, J. Duque, “A text book for Digital Circuits” (Original Title: Circuitos Digitales). ed: Ediciones Tecnologica de Bolivar ISBN: 9589745946 v. 1 pages. 143. Colombia, 2004 – Language: Spanish</div>

Jcmartinez http://nueess.coe.neu.edu/nueess/index.php/Juan_Carlos_Martinez_Santos 2012-03-28T17:25:46Z

<p>Jcmartinez:&#32;/* Education */</p> <hr /> <div>[[image:Juan-photo.jpg|thumb|200px|left]]<br /> '''Juan Carlos Martinez Santos'''<br /> <br /> Ph.D Candidate<br /> <br /> Department of Electrical and Computer Engineering<br /> <br /> University of Connecticut<br /> <br /> 371 Fairfield Way, U-2157<br /> <br /> Storrs, CT 06269-2157, USA<br /> <br /> Email: jsm07006 AT engr.uconn.edu<br /> <br /> Webpage: http://laurel.engr.uconn.edu/~jcmartin<br /> <br /> == Education ==<br /> *Ph.D. Candidate: [http://www.ece.neu.edu/ece Dept. of Electrical and Computer Engineering], [http://www.northeastern.edu/ Northeastern University], USA, 2012 (expected)<br /> :Advisor: [http://www.engr.uconn.edu/~yfei Prof. Yunsi Fei]<br /> <br /> *M.Sc and B.S.: [http://www.uis.edu.co/webUIS/es/academia/facultades/fisicoMecanicas/escuelas/e3t/ Escuela de Ingenierias Electrica, Electronica y Telecomunicaciones], [http://www.uis.edu.co/webUIS/en/index.html Universidad Industrial de Santander], Bucaramanga, Santander - Colombia, 2004 - 2001<br /> <br /> == Research ==<br /> *[DIFT for multi-thread applications on multi-core architectures]<br /> *[Dynamic Information Flow Tracking]<br /> *[Anomalous Path Detection]<br /> <br /> == Publications ==<br /> '' Journal Papers''<br /> *J. C. Martinez Santos, S. H. Contreras Ortiz, “Tele-operated Laboratory for Digital Systems Design” (Original Title: Laboratorio Tele-operado de Técnicas Digitales), in Revista Colombiana De Tecnologías De Avanzada, ISSN: 1692-7257 ed: Java Eu v.6 fasc. p.92 – 96. Colombia, 2005 – Language: Spanish<br /> *J. C. Martinez Santos, J. H. Ramon Suarez, “Teaching Digital Systems Design using Hardware Description Languages” (Original Title: Enseñanza de Sistemas Digitales usando lenguajes de descripción de hardware), in UIS Ingenierías ISSN: 1657-4583 ed: Publicaciones UIS v.2 fasc.1 p.35 – 39. Colombia ,2003 – Language: Spanish<br /> <br /> '' Conference Papers ''<br /> *J. C. Martinez Santos, Y. Fei, and Z. J. Shi, “PIFT: Efficient dynamic information flow tracking using secure page allocation,” in WkShp on Embedded System Security (WESS) (held in conjunction with Embedded Systems Week), Oct. 2009.<br /> *J. C. Martinez Santos and Y. Fei, “Leveraging speculative architectures for run-time program validation,” in Proc. IEEE Int. Conf. Computer Design, Oct. 2008.<br /> *J. C. Martinez Santos, L. S. Silva Lopez, “A Platform for Developing Skills on Implementation of Wireless Sensor Networks Using Active Learning”, in Active Learning on Engineering, Universidad de Los Andes, p.205 - 206, Bogota, Colombia, 2008<br /> *J. C. Martinez Santos, L. S. Silva Lopez, O. G. Erazo Cruz, “A Study Case: a WSN using IEE and MAC SMAC hardware with adjustable duty cycle for improving battery life time” (Original Title: El caso de una WSN empleando Hardware IEE y MAC SMAC, con variación de ciclos de trabajo para mejorar vida de Baterías), in Proc. i2ComM . ISBN: 9789588375 ed: I2COMM, p.122 - 127, Colombia 2008 – Language: Spanish<br /> *J. C. Martinez Santos, L. S. Silva Lopez, E. Ospina Mateus, “Analysis of a WSN inside of a car using the IEEE 802.15.4 standard with adjustable duty cycle for improving battery life time” (Original Title: Análisis de una WSN en un Automóvil bajo IEEE 802.15.4 con Variación de Ciclos de Trabajo para Mejorar Vida de Baterías), in IEEE Colcom 2007, Congreso Colombiano De Comunicaciones . ISBN: 978-958-44, Colombia, 2007 – Language: Spanish<br /> *J. C. Martinez Santos, S. H. Contreras Ortiz, E. Gomez Vasquez, O. Acevedo Patiño, “LABTO: Teleoperated Laboratory of Digital Systems Design” (Original Title: LABTO: Laboratorio TeleOperado de Tecnicas Digitales), in IEEE Colombian Workshop on Circuits and Systems , ISBN: 978-958-69 ed: Universidad De Los Andes. Colombia, 2006 – Language: Spanish<br /> *J. C. Martinez Santos, O. S. Bayter Fontalvo, “Total Harmonic Distortion meter using a Digital Signal Processor” (Original Title: Medidor de Distorsión Armónica Total basado en un Procesador Digital de Señales), in XI Simposio de Tratamiento de Señales, Imagenes y vision Artificial. . ISBN: 958-683-93 ed: Sociedad Colombiana de Tratamiento de Señales , v. I. Colombia, 2006 – Language: Spanish<br /> *J. C. Martinez Santos, S. H. Contreras Ortiz, E. Gomez Vasquez, O. Acevedo Patiño, “Tele-operated laboratory of Digital systems Desing” (Original Title: Laboratorio Tele-operado de Técnicas Digitales), in XXIV Reunión Nacional de Facultades de Ingeniería. ISBN: 958-608-049-8, p.195 – 199. Colombia, 2004 – Language: Spanish<br /> <br /> '' Books ''<br /> *J. C. Martinez Santos, J. Duque, “A text book for Digital Circuits” (Original Title: Circuitos Digitales). ed: Ediciones Tecnologica de Bolivar ISBN: 9589745946 v. 1 pages. 143. Colombia, 2004 – Language: Spanish</div>

Jcmartinez http://nueess.coe.neu.edu/nueess/index.php/Tiansi_Hu 2012-03-28T17:25:19Z

<p>Jcmartinez:&#32;/* Education */</p> <hr /> <div>'''Tiansi Hu'''<br /> <br /> Ph.D Candidate<br /> <br /> Department of Electrical and Computer Engineering<br /> <br /> Northeastern University<br /> <br /> 360 Huntington Avenue<br /> <br /> Boston, MA 02115<br /> <br /> Email: tiansi AT ece.neu.edu<br /> <br /> <br /> == Education ==<br /> *Ph.D. Candidate: [http://www.ece.neu.edu/ece Dept. of Electrical and Computer Engineering], [http://www.northeastern.edu/ Northeastern University], USA, 2012 (expected)<br /> :Advisor: [http://www.ece.neu.edu/ece/index.php/component/content/170?task=view Prof. Yunsi Fei]<br /> <br /> *M.S.: [http://www.engr.uconn.edu/ece Dept. of Electrical and Computer Engineering], [http://www.uconn.edu University of Connecticut], USA, 2011<br /> <br /> *B.S.: [http://eecs.pku.edu.cn School of Electronics and Computer Science], [http://www.pku.edu.cn Peking University], China, 2007<br /> <br /> == Research ==<br /> *Energy efficiency design for wireless sensor networks<br /> *Protocols in underwater sensor networks<br /> *Delay tolerant networks<br /> <br /> == Publications ==<br /> *{{#lst:Publications|thc4}}<br /> *{{#lst:Publications|hlj3}}<br /> *{{#lst:Publications|thc3}}<br /> *{{#lst:Publications|thc2}}<br /> *{{#lst:Publications|thj1}}<br /> *P. Xie, Z. Zhou, Z. Peng, H. Yan, T. Hu, J.-H. Cui, Z. Shi, Y. Fei, and S. Zhou, Aqua-Sim: An NS-2 Based Simulator for Underwater Sensor Networks, IEEE/MTS Oceans 2009, Biloxi, Mississippi, Oct 2009.<br /> *{{#lst:Publications|thc1}}<br /> *T. Hu, X. Zheng, and Y. Sun, “Design and Implementation of Multimedia Communication Terminal,” Intel Cup Embedded System Design Invitational Contest, Jul, 2006</div>

Jcmartinez